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  • 11
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    The split-cross-bridge resistor for measuring the sheet resistance, linewidth, and line spacing of conducting layers (1986)
    In:  Other Sources
    Details
    Publication Date: 2011-08-19
    Description: A new test structure was developed for evaluating the line spacing between conductors on the same layer using an electrical measurement technique. This compact structure can also be used to measure the sheet resistance, linewidth, and line pitch of the conducting layer. Using an integrated-circuit fabrication process, this structure was fabricated in diffused polycrystalline silicon and metal layers and measured optically and electrically. For the techniques used, the optical measurements were typically one-quarter micron greater than the electrical measurements. Most electrically measured line pitch values were within 2 percent of the designed value. A small difference between the measured and designed line pitch is used to validate sheet resistance, linewidth, and line spacing values.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Transactions on Electron Devices (ISSN 0018-9383); ED-33; 1572-157
    Format: text
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    NASA TECHNICAL REPORTS
  • 12
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    Propagation delay measurements from a timing sampler intended for use in space (1987)
    In:  Other Sources
    Details
    Publication Date: 2011-08-19
    Description: A 3-micron CMOS timing sampler is described which is a test circuit designed into the Jet Propulsion Labs' CRRES chip to be flown on the Combined Release and Radiation Effects Satellite (CRRES). The timing sampler consists of 64 inverter-pair stages with sampling latches and decoder circuitry. The sampler is used to measure inverter-pair propagation delays, which are nominally 2.5 ns, with a resolution of 100 ps. A simple model was developed to explain the radiation-induced inverter-pair delay shifts in terms of radiation-induced MOSFET threshold-voltage shifts and effective modal capacitances. The magnitude of the shift in pair delay with radiation was estimated at the point where the n-MOSFET threshold voltage became zero. For a 0.7-V-threshold shift, the pair delay increased from its preradiation value by 360 ps for a rising step input and decreased by 190 ps for a falling step input.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Transactions on Nuclear Science (ISSN 0018-9499); NS-34; 1470-147
    Format: text
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    NASA TECHNICAL REPORTS
  • 13
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    A CMOS matrix for extracting MOSFET parameters before and after irradiation (1988)
    In:  Other Sources
    Details
    Publication Date: 2011-08-19
    Description: An addressable matrix of 16 n- and 16 p-MOSFETs was designed to extract the dc MOSFET parameters for all dc gate bias conditions before and after irradiation. The matrix contains four sets of MOSFETs, each with four different geometries that can be biased independently. Thus the worst-case bias scenarios can be determined. The MOSFET matrix was fabricated at a silicon foundry using a radiation-soft CMOS p-well LOCOS process. Co-60 irradiation results for the n-MOSFETs showed a threshold-voltage shift of -3 mV/krad(Si), whereas the p-MOSFETs showed a shift of 21 mV/krad(Si). The worst-case threshold-voltage shift occurred for the n-MOSFETs, with a gate bias of 5 V during the anneal. For the p-MOSFETs, biasing did not affect the shift in the threshold voltage. A parasitic MOSFET dominated the leakage of the n-MOSFET biased with 5 V on the gate during irradiation. Co-60 test results for other parameters are also presented.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Transactions on Nuclear Science (ISSN 0018-9499); 35; 1529-153
    Format: text
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    NASA TECHNICAL REPORTS
  • 14
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    Radiation dependence of inverter propagation delay from timing sampler measurements (1989)
    In:  Other Sources
    Details
    Publication Date: 2011-08-19
    Description: A timing sampler consisting of 14 four-stage inverter-pair chains with different load capacitances was fabricated in 1.6-micron n-well CMOS and irradiated with cobalt-60 at 10 rad(Si)/s. For this CMOS process the measured results indicate that the rising delay increases by about 2.2 ns/Mrad(Si) and the falling delay increase is very small, i.e., less than 300 ps/Mrad(Si). The amount of radiation-induced delay depends on the size of the load capacitance. The maximum value observed for this effect was 5.65 ns/pF-Mrad(Si). Using a sensitivity analysis, the sensitivity of the rising delay to radiation can be explained by a simple timing model and the radiation sensitivity of dc MOSFET parameters. This same approach could not explain the insensitivity of the falling delay to radiation. This may be due to a failure of the timing model and/or trapping effects.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Transactions on Nuclear Science (ISSN 0018-9499); 36; 1981-198
    Format: text
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    NASA TECHNICAL REPORTS
  • 15
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    Test chips for custom ICs - Six kinds of test structures (1982)
    In:  Other Sources
    Details
    Publication Date: 2011-08-18
    Description: Microelectronic test chips contain a number of test structures that are used for a variety of purposes in fabricating integrated circuits. For convenience, their use is divided into six groups: layout-rule evaluating, process-parameter extraction, device-parameter extraction, circuit-parameter extraction, initial-fabrication failure analysis, and reliability failure analysis. A given test structure can be used to gather information in a number of these groups. Examples are given here of the kinds of parameters that can be obtained in each of these groups. A table is included summarizing various device failures common to bulk CMOS and indicating failure mechanisms appearing after wafer fabrication and after stress.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Circuits Manufacturing; June 198
    Format: text
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    NASA TECHNICAL REPORTS
  • 16
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    Parameter extraction from spaceborne MOSFETs (1985)
    In:  Other Sources
    Details
    Publication Date: 2011-08-19
    Description: An addressable matrix of 32 CMOS transistors was designed into a test chip to be flown on the Combined Release and Radiation Effects Satellite (CRRES). In this paper the matrix is described along with a SPICE-like parameter extraction procedure called JMOSFIT, and Cobalt 60 radiation test results are presented that illustrate the shift in the 21-MOSFET parameters derived from JMOSFIT.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Transactions on Nuclear Science (ISSN 0018-9499); NS-32; 4237-424
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    NASA TECHNICAL REPORTS
  • 17
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    Off-line, built-in test techniques for VLSI circuits (1982)
    In:  Other Sources
    Details
    Publication Date: 2011-08-18
    Description: It is shown that the use of redundant on-chip circuitry improves the testability of an entire VLSI circuit. In the study described here, five techniques applied to a two-bit ripple carry adder are compared. The techniques considered are self-oscillation, self-comparison, partition, scan path, and built-in logic block observer. It is noted that both classical stuck-at faults and nonclassical faults, such as bridging faults (shorts), stuck-on x faults where x may be 0, 1, or vary between the two, and parasitic flip-flop faults occur in IC structures. To simplify the analysis of the testing techniques, however, a stuck-at fault model is assumed.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Computer; June 198
    Format: text
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    NASA TECHNICAL REPORTS
  • 18
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    Alpha-particle sensitive test SRAMs (1990)
    In:  Other Sources
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    Publication Date: 2011-08-19
    Description: A bench-level test is being developed to evaluate memory-cell upsets in a test SRAM designed with a cell offset voltage. This offset voltage controls the critical charge needed to upset the cell. The effect is demonstrated using a specially designed 2-micron n-well CMOS 4-kb test SRAM and a Po-208 5.1-MeV 0.61-LET alpha-particle source. This test SRAM has been made sensitive to alpha particles through the use of a cell offset voltage, and this has allowed a bench-level characterization in a laboratory setting. The experimental data are linked to a alpha-particle interaction physics and to SPICE circuit simulations through the alpha-particle collection depth. The collection depth is determined by two methods and found to be about 7 micron. In addition, alpha particles that struck outside the bloated drain were able to flip the SRAM cells. This lateral charge collection was observed to be more than 6 micron.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Transactions on Nuclear Science (ISSN 0018-9499); 37; 1849-185
    Format: text
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    NASA TECHNICAL REPORTS
  • 19
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    Test chips and ASIC qualification (1991)
    In:  CASI
    Details
    Publication Date: 2013-08-29
    Description: A test chip set being developed to aid in the qualification of spaceborne Application Specific Integrated Circuits (ASICs) is described. The chip set consists of a process monitor for process parameter verification, a fault chip for yield analysis, a reliability chip for ASIC failure rate analysis, and total ionizing dose and single event upset chips for radiation effect analysis. The test structures contained in these chips are discussed along with representative test results.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: ESA, ESA Electronic Components Conference; p 221-226
    Format: text
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    NASA TECHNICAL REPORTS
  • 20
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    SEU/SRAM as a Process Monitor (1993)
    In:  Other Sources
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    Publication Date: 2018-06-08
    Description: The SEU/SRAM is a 4-kbit Static Random Access Memory (SRAM) designed to detect Single-Event Upsets (SEUs) produced by high energy particles. This device was used to determine the distribution in the memory cell spontaneous flip potential.
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    NASA TECHNICAL REPORTS
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