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  • 1
    Publication Date: 2019-06-28
    Description: Collection of design and testing procedures partly automates development of built-in test chips for CMOS integrated circuits. Testchip methodology intended especially for users of custom integratedcircuit wafers. Test-Chip Designs and Testing Procedures (including datareduction procedures) generated automatically by computer from programed design and testing rules and from information supplied by user.
    Keywords: ELECTRONIC SYSTEMS
    Type: NPO-15988 , NASA Tech Briefs (ISSN 0145-319X); 9; 1; P. 64
    Format: text
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