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  • 1
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    Microwave Spin Resonance Absorption by Conduction Electrons in Metallic Sodium (1952)
    American Physical Society
    Details
    Publication Date: 1952-11-15
    Print ISSN: 0031-899X
    Electronic ISSN: 1536-6065
    Topics: Physics
    Published by American Physical Society
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    PAPER CURRENT
  • 2
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    Ulysses: A functional description and simulation software system (1986)
    In:  CASI
    Details
    Publication Date: 2006-02-14
    Description: Current design tools for digital circuits and systems are not well-integrated among the behavioral, gate, and transistor levels of design. Ulysses is a prototype software system that consists of a description language, a description compiler, and a simulator that make no distinction among these levels. The language is uniform over the entire range of logical descriptions, the description is hierarchical with no fundamental restrictions on depth or mixing of levels, and the simulator is fully integrated with the description. The structure of the language, compiler, and simulator are described in terms of their relationships to the abstractions of physical systems that are made in order to create logical descriptions and models of behavior.
    Keywords: COMPUTER PROGRAMMING AND SOFTWARE
    Type: The Telecommunications and Data Acquisition Report (date]; p 193 - 202
    Format: text
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    NASA TECHNICAL REPORTS
  • 3
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    Pinhole array capacitor for oxide integrity analysis (1985)
    In:  CASI
    Details
    Publication Date: 2006-02-14
    Description: The integrity of the metal-poly oxide and the gate oxide was evaluated for several 5-micron CMOS-bulk process. The pinhole array capacitor consists of diffused and poly fingers that form a network of MOS transistors (elements), which are capped by a deposited oxide and metal layer. The smallest structure used contained about 15,000 elements and the largest structure contained about 68,000 elements. Each structure was divided into several subarrays. The structures are placed a number of times on each wafer. From a yield analysis of the subarrays, the elements per defect were found to be typically in excess of 50,000 elements/defect for the metal-poly oxide and 100,000 elements/defect for the gate oxide. From the switching behavior of the transistors, the gate oxide defects were tentatively identified as gate-to-body shorts rather than gate-to-diffusion shorts.
    Keywords: INSTRUMENTATION AND PHOTOGRAPHY
    Type: Product Assurance Technology for Custom LSI(VLSI Electronics; 7 p
    Format: text
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    NASA TECHNICAL REPORTS
  • 4
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    Test chips for custom ICs - Six kinds of test structures (1982)
    In:  Other Sources
    Details
    Publication Date: 2011-08-18
    Description: Microelectronic test chips contain a number of test structures that are used for a variety of purposes in fabricating integrated circuits. For convenience, their use is divided into six groups: layout-rule evaluating, process-parameter extraction, device-parameter extraction, circuit-parameter extraction, initial-fabrication failure analysis, and reliability failure analysis. A given test structure can be used to gather information in a number of these groups. Examples are given here of the kinds of parameters that can be obtained in each of these groups. A table is included summarizing various device failures common to bulk CMOS and indicating failure mechanisms appearing after wafer fabrication and after stress.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Circuits Manufacturing; June 198
    Format: text
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    NASA TECHNICAL REPORTS
  • 5
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    Portable design rules for bulk CMOS (1982)
    In:  Other Sources
    Details
    Publication Date: 2011-08-18
    Description: It is pointed out that for the past several years, one school of IC designers has used a simplified set of nMOS geometric design rules (GDR) which is 'portable', in that it can be used by many different nMOS manufacturers. The present investigation is concerned with a preliminary set of design rules for bulk CMOS which has been verified for simple test structures. The GDR are defined in terms of Caltech Intermediate Form (CIF), which is a geometry-description language that defines simple geometrical objects in layers. The layers are abstractions of physical mask layers. The design rules do not presume the existence of any particular design methodology. Attention is given to p-well and n-well CMOS processes, bulk CMOS and CMOS-SOS, CMOS geometric rules, and a description of the advantages of CMOS technology.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: VLSI Design; 1982
    Format: text
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    NASA TECHNICAL REPORTS
  • 6
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    Test Pattern for IC's (1983)
    In:  Other Sources
    Details
    Publication Date: 2019-06-28
    Description: Random-fault densities measured in array of standard structures. Test pattern is array of standard circuit elements built into circuit chip along with, or in lieu of, integrated circuit objective process. Measurements on ray made and interpreted so fabrication process can be corrected as necessary.
    Keywords: FABRICATION TECHNOLOGY
    Type: NPO-15648 , NASA Tech Briefs (ISSN 0145-319X); 7; 4; P. 473
    Format: text
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    NASA TECHNICAL REPORTS
  • 7
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    Designing Test Chips for Custom Integrated Circuits (1985)
    In:  Other Sources
    Details
    Publication Date: 2019-06-28
    Description: Collection of design and testing procedures partly automates development of built-in test chips for CMOS integrated circuits. Testchip methodology intended especially for users of custom integratedcircuit wafers. Test-Chip Designs and Testing Procedures (including datareduction procedures) generated automatically by computer from programed design and testing rules and from information supplied by user.
    Keywords: ELECTRONIC SYSTEMS
    Type: NPO-15988 , NASA Tech Briefs (ISSN 0145-319X); 9; 1; P. 64
    Format: text
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    NASA TECHNICAL REPORTS
  • 8
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    Pinhole array capacitor for oxide integrity analysis (1983)
    In:  Other Sources
    Details
    Publication Date: 2019-06-28
    Description: The integrity of the metal-poly oxide and the gate oxide was evaluated for several 5-micron CMOS-bulk processes. The pinhole array capacitor consists of diffused and poly fingers that form a network of MOS transistors (elements), which are capped by a deposited oxide and metal layer. The smallest structure used in this study contained about 15,000 elements and the largest structure contained about 68,000 elements. Each structure was divided into several subarrays. The structures are placed a number of times on each wafer. From a yield analysis of the subarrays, the elements per defect were found to be typically in excess of 50,000 elements/defect for the metal-poly oxide and 100,000 elements/defect for the gate oxide. From the switching behavior of the transistors, the gate oxide defects were tentatively identified as gate-to-body shorts rather than gate-to-diffusion shorts.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Solid State Technology (ISSN 0038-111X); 26; 131-137
    Format: text
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    NASA TECHNICAL REPORTS
  • 9
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    Migratory gold resistive shorts - Chemical aspects of a failure mechanism (1975)
    In:  Other Sources
    Details
    Publication Date: 2019-07-13
    Description: Integrated-circuit devices using the Ti/W/Au metal system are subject to failure mechanisms based on electrolytic corrosion. The migratory gold resistive short (MGRS) failure mode is one example of this mechanism and results in the formation of filamentary or dendritic deposits of gold between adjacent stripes on the IC chip. This reaction requires the presence of a sufficient amount of water, a bias voltage between adjacent stripes, and the activation of the cathodic (-) stripe. Gold ions are transported from anode to cathode through a film of moisture adsorbed on the surface of the chip; halide ions are probably involved in the transfer. Their presence is verified experimentally by X-ray photoelectron spectroscopy. Some of the chemical and electrostatic factors involved in the MGRS mechanism are discussed in this paper, including the questions of a threshold level of moisture and contamination.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Annual Symposium on Reliability physics 1975; Apr 01, 1975 - Apr 03, 1975; Las Vegas, NV
    Format: text
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    NASA TECHNICAL REPORTS
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