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  • 1
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    In-Situ Planetary Chemical Analysis (2000)
    In:  CASI
    Details
    Publication Date: 2004-12-03
    Description: Both, the search for evidence of life on Mars and the assessment of the Martian environment in respect to its compatibility with human explorers, will require the ability to measure and understand the aqueous chemistry of the Martian regolith. Direct in-situ chemical analysis is the only method by which chemical biosignatures can be reliably recognized and the toxicity of the regolith accurately assessed. Qualitative and quantitative determination of the aqueous ionic constituents and their concentrations is critical in developing kinetic and thermodynamic models that can be used to accurately predict the potential of the past or present Martian geochemical environment to have either generated or still sustain life. In-situ chemical characterization could provide evidence as to whether the chemical composition of the regolith or evaporates in suspected ancient water bodies have been biologically influenced.
    Keywords: Lunar and Planetary Science and Exploration
    Type: Concepts and Approaches for Mars Exploration; Part 1; 184-185; LPI-Contrib-1062-Pt-1
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    NASA TECHNICAL REPORTS
  • 2
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    Fault models (1985)
    In:  CASI
    Details
    Publication Date: 2006-02-14
    Description: A major problem in the qualification of integrated circuit cells and in the development of adequate tests for the circuits is to lack of information on the nature and density of fault models. Some of this information is being obtained from the test structures. In particular, the Pinhole Array Capacitor is providing values for the resistance of gate oxide shorts, and the Addressable Inverter Matrix is providing values for parameter distributions such as noise margins. Another CMOS fault mode, that of the open-gated transistor, is examined and the state of the transistors assessed. Preliminary results are described for a number of open-gated structures such as transistors, inverters, and NAND gates. Resistor faults are applied to various CMOS gates and the time responses are noted. The critical value for the resistive short to upset the gate response was determined.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Product Assurance Technology for Custom LSI(VLSI Electronics p; 6 p
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  • 3
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    JMOSFET: A MOSFET parameter extractor with geometry-dependent terms (1985)
    In:  CASI
    Details
    Publication Date: 2006-02-14
    Description: The parameters from metal-oxide-silicon field-effect transistors (MOSFETs) that are included on the Combined Release and Radiation Effects Satellite (CRRES) test chips need to be extracted to have a simple but comprehensive method that can be used in wafer acceptance, and to have a method that is sufficiently accurate that it can be used in integrated circuits. A set of MOSFET parameter extraction procedures that are directly linked to the MOSFET model equations and that facilitate the use of simple, direct curve-fitting techniques are developed. In addition, the major physical effects that affect MOSFET operation in the linear and saturation regions of operation for devices fabricated in 1.2 to 3.0 mm CMOS technology are included. The fitting procedures were designed to establish single values for such parameters as threshold voltage and transconductance and to provide for slope matching between the linear and saturation regions of the MOSFET output current-voltage curves. Four different sizes of transistors that cover a rectangular-shaped region of the channel length-width plane are analyzed.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Product Assurance Technology for Custom LSI(VLSI Electronics; 42 p
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  • 4
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    Pinhole array capacitor for oxide integrity analysis (1985)
    In:  CASI
    Details
    Publication Date: 2006-02-14
    Description: The integrity of the metal-poly oxide and the gate oxide was evaluated for several 5-micron CMOS-bulk process. The pinhole array capacitor consists of diffused and poly fingers that form a network of MOS transistors (elements), which are capped by a deposited oxide and metal layer. The smallest structure used contained about 15,000 elements and the largest structure contained about 68,000 elements. Each structure was divided into several subarrays. The structures are placed a number of times on each wafer. From a yield analysis of the subarrays, the elements per defect were found to be typically in excess of 50,000 elements/defect for the metal-poly oxide and 100,000 elements/defect for the gate oxide. From the switching behavior of the transistors, the gate oxide defects were tentatively identified as gate-to-body shorts rather than gate-to-diffusion shorts.
    Keywords: INSTRUMENTATION AND PHOTOGRAPHY
    Type: Product Assurance Technology for Custom LSI(VLSI Electronics; 7 p
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  • 5
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    Addressable inverter matrix for process and device characterization (1985)
    In:  CASI
    Details
    Publication Date: 2006-02-14
    Description: The addressable inverter matrix consists of 222 inverters each accessible with the aid of a shift register. The structure has proven useful in characterizing the variability of inverter transfer curves and in diagnosing processing faults. For good 3-micron CMOS bulk inverters investigated, the percent standard deviation of the inverter threshold voltage was less than one percent and the inverter gain (the slope of the inverter transfer curve at the inverter threshold vltage) was less than 3 percent. The average noise margin for the inverters was near 2 volts for a power supply voltage of 5 volts. The specific faults studied included undersize pull-down transistor widths and various open contacts in the matrix.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Product Assurance Technology for Custom LSI(VLSI Electronics; 7 p
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  • 6
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    Bench-level characterization of a CMOS standard-cell D-latch using alpha-particle sensitive test circuits (1991)
    In:  Other Sources
    Details
    Publication Date: 2011-08-24
    Description: A methodology is described for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. Measurements were made on a 1.6-micron n-well CMOS 4-kb test SRAM irradiated with an Am-241 alpha-particle source. A collection depth of 6.09 micron was determined using these results and TRIM computer code. Using this collection depth and SPICE derived critical charge results on the latch design, an LET threshold of 34 MeV sq cm/mg was predicted. Heavy ion tests were then performed on the latch and an LET threshold of 41 MeV sq cm/mg was determined.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Transactions on Nuclear Science (ISSN 0018-9499); 38; 1486-149
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    NASA TECHNICAL REPORTS
  • 7
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    The split-cross-bridge resistor for measuring the sheet resistance, linewidth, and line spacing of conducting layers (1986)
    In:  Other Sources
    Details
    Publication Date: 2011-08-19
    Description: A new test structure was developed for evaluating the line spacing between conductors on the same layer using an electrical measurement technique. This compact structure can also be used to measure the sheet resistance, linewidth, and line pitch of the conducting layer. Using an integrated-circuit fabrication process, this structure was fabricated in diffused polycrystalline silicon and metal layers and measured optically and electrically. For the techniques used, the optical measurements were typically one-quarter micron greater than the electrical measurements. Most electrically measured line pitch values were within 2 percent of the designed value. A small difference between the measured and designed line pitch is used to validate sheet resistance, linewidth, and line spacing values.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Transactions on Electron Devices (ISSN 0018-9383); ED-33; 1572-157
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  • 8
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    Propagation delay measurements from a timing sampler intended for use in space (1987)
    In:  Other Sources
    Details
    Publication Date: 2011-08-19
    Description: A 3-micron CMOS timing sampler is described which is a test circuit designed into the Jet Propulsion Labs' CRRES chip to be flown on the Combined Release and Radiation Effects Satellite (CRRES). The timing sampler consists of 64 inverter-pair stages with sampling latches and decoder circuitry. The sampler is used to measure inverter-pair propagation delays, which are nominally 2.5 ns, with a resolution of 100 ps. A simple model was developed to explain the radiation-induced inverter-pair delay shifts in terms of radiation-induced MOSFET threshold-voltage shifts and effective modal capacitances. The magnitude of the shift in pair delay with radiation was estimated at the point where the n-MOSFET threshold voltage became zero. For a 0.7-V-threshold shift, the pair delay increased from its preradiation value by 360 ps for a rising step input and decreased by 190 ps for a falling step input.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Transactions on Nuclear Science (ISSN 0018-9499); NS-34; 1470-147
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  • 9
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    A CMOS matrix for extracting MOSFET parameters before and after irradiation (1988)
    In:  Other Sources
    Details
    Publication Date: 2011-08-19
    Description: An addressable matrix of 16 n- and 16 p-MOSFETs was designed to extract the dc MOSFET parameters for all dc gate bias conditions before and after irradiation. The matrix contains four sets of MOSFETs, each with four different geometries that can be biased independently. Thus the worst-case bias scenarios can be determined. The MOSFET matrix was fabricated at a silicon foundry using a radiation-soft CMOS p-well LOCOS process. Co-60 irradiation results for the n-MOSFETs showed a threshold-voltage shift of -3 mV/krad(Si), whereas the p-MOSFETs showed a shift of 21 mV/krad(Si). The worst-case threshold-voltage shift occurred for the n-MOSFETs, with a gate bias of 5 V during the anneal. For the p-MOSFETs, biasing did not affect the shift in the threshold voltage. A parasitic MOSFET dominated the leakage of the n-MOSFET biased with 5 V on the gate during irradiation. Co-60 test results for other parameters are also presented.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Transactions on Nuclear Science (ISSN 0018-9499); 35; 1529-153
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  • 10
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    Radiation dependence of inverter propagation delay from timing sampler measurements (1989)
    In:  Other Sources
    Details
    Publication Date: 2011-08-19
    Description: A timing sampler consisting of 14 four-stage inverter-pair chains with different load capacitances was fabricated in 1.6-micron n-well CMOS and irradiated with cobalt-60 at 10 rad(Si)/s. For this CMOS process the measured results indicate that the rising delay increases by about 2.2 ns/Mrad(Si) and the falling delay increase is very small, i.e., less than 300 ps/Mrad(Si). The amount of radiation-induced delay depends on the size of the load capacitance. The maximum value observed for this effect was 5.65 ns/pF-Mrad(Si). Using a sensitivity analysis, the sensitivity of the rising delay to radiation can be explained by a simple timing model and the radiation sensitivity of dc MOSFET parameters. This same approach could not explain the insensitivity of the falling delay to radiation. This may be due to a failure of the timing model and/or trapping effects.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Transactions on Nuclear Science (ISSN 0018-9499); 36; 1981-198
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