Publication Date:
2019-07-13
Description:
A single event upset (SEU)-hardened flip-flop has been designed and developed for antifuse Field Programmable Gate Array (FPGA) application. Design and application issues, testability, test methods, simulation, and results are discussed.
Keywords:
Electronics and Electrical Engineering
Type:
IEEE NSREC 2001; Jul 01, 2001; British Columbia; Canada
Format:
application/pdf
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