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A SEU-Hard Flip-Flop for Antifuse FPGAsA single event upset (SEU)-hardened flip-flop has been designed and developed for antifuse Field Programmable Gate Array (FPGA) application. Design and application issues, testability, test methods, simulation, and results are discussed.
Document ID
20010069271
Acquisition Source
Goddard Space Flight Center
Document Type
Preprint (Draft being sent to journal)
Authors
Katz, R. (NASA Goddard Space Flight Center Greenbelt, MD United States)
Wang, J. J. (Actel Corp. Sunnyvale, CA United States)
McCollum, J. (Actel Corp. Sunnyvale, CA United States)
Cronquist, B. (Actel Corp. Sunnyvale, CA United States)
Chan, R. (Actel Corp. Sunnyvale, CA United States)
Yu, D. (Actel Corp. Sunnyvale, CA United States)
Kleyner, I. (Orbital Sciences Corp. Greenbelt, MD United States)
Day, John H.
Date Acquired
September 7, 2013
Publication Date
January 1, 2001
Subject Category
Electronics And Electrical Engineering
Meeting Information
Meeting: IEEE NSREC 2001
Location: British Columbia
Country: Canada
Start Date: July 1, 2001
Sponsors: Institute of Electrical and Electronics Engineers
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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