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  • Articles  (9)
  • CMOS  (9)
  • 2020-2022
  • 2000-2004  (9)
  • Electrical Engineering, Measurement and Control Technology  (9)
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  • Articles  (9)
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  • 1
    Electronic Resource
    Electronic Resource
    Springer
    Analog integrated circuits and signal processing 25 (2000), S. 253-259 
    ISSN: 1573-1979
    Keywords: CMOS ; GSM ; transmitter ; PLL
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper describes a CMOS offset phase locked loop (OPLL) for a global system for mobile communications (GSM) transmitter. The OPLL is a PLL with a down-conversion mixer in the feedback path and is used in the transmit (Tx) path as a frequency converter. It has a tracking bandpass filter characteristic in such a way that the OPLL can suppress the noise in the GSM receiving band (Tx noise) without a duplexer. When the loop bandwidth of the OPLL was 1.0 MHz, the Tx noise level of −163.5 dBc/Hz, the phase error of 0.66° rms, and the settling time of 40 μs were achieved. The IC was implemented by using 0.35-μm CMOS process. It takes 860 μm×620 μm of total chip area and consumes 17.6 mA with a 3.0 V power supply.
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  • 2
    Electronic Resource
    Electronic Resource
    Springer
    Analog integrated circuits and signal processing 22 (2000), S. 209-220 
    ISSN: 1573-1979
    Keywords: low-voltage ; low-power ; log-domain ; CMOS ; filters ; current-mode ; translinear
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A design technique for low-voltage, micropower continuous-time filters implementing CMOS devices operating in weak inversion is presented. The basic building block is the CMOS log-domain integrator. The effects of the MOS device nonidealities on the integrator are investigated and verified by HSPICE simulations. A 5th-order Chebyshev lowpass ladder filter was designed and simulated. The filter operates with low supply voltage of 1.5 V to achieve a cutoff frequency tunable range of 100 Hz–100 kHz, and it has a power dissipation of 254 nW/pole at the cutoff frequency of 100 kHz. The filter was laid out using the 0.35-μm mixed-mode polycide CMOS technology and occupies a die area of 0.04 mm2 without the i/o pads
    Type of Medium: Electronic Resource
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  • 3
    ISSN: 1573-1979
    Keywords: transceiver ; CMOS ; front-end ; wireless ; RF
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This work describes the design and realization of a low voltage single-chip wireless transceiver front-end in a standard 0.25 μm CMOS technology. The presented prototype integrates the LNA, down-converters, VCO, quadrature generator, up-converter and pre-amplifier on a single die. A high level of integration is achieved by using a low-IF topology for reception, a direct quadrature up-conversion topology for transmission and an oscillator with on-chip integrated inductor. The final objective of this design is to develop a complete transceiver system for wireless communications at 1.8 GHz that can be built with a minimum of surrounding components: only an antenna, a duplexer, a power amplifier and a baseband signal processing chip. The presented circuit consumes 240 mW from a 2.5 V supply and occupies a die area of 8.6 mm2.
    Type of Medium: Electronic Resource
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  • 4
    Electronic Resource
    Electronic Resource
    Springer
    Analog integrated circuits and signal processing 22 (2000), S. 41-49 
    ISSN: 1573-1979
    Keywords: A/D converter ; pipeline ; high-speed ; WCDMA ; CMOS
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper describes an 8-bit 40 MS/s pipeline A/D converter suitable for WCDMA receiver applications. Small power consumption is achieved by using 1.5 bit/stage pipeline architecture and by scaling the capacitor values along the converter. Digital correction allows also to use very low power dynamic comparators. The multiplying D/A converters (MDACs) utilize a modified folded cascode amplifier. The circuit is designed and fabricated in a 0.5 μm CMOS technology. The measured DNL is 0.85 LSB and INL 1.91 LSB. The converter achieves over 48 dBc SFDR and more than 41 dBc SNDR dissipating 61 mW from a 2.7 V supply.
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  • 5
    Electronic Resource
    Electronic Resource
    Springer
    Analog integrated circuits and signal processing 25 (2000), S. 35-46 
    ISSN: 1573-1979
    Keywords: low-voltage ; log-domain ; CMOS ; integrater ; filters ; current-mode ; translinear
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A new fully differential class-AB log-domain integrator is proposed. The structure consists of two non-inverting integrators and an intersection circuit with a common-feedback circuit. The effects of transistor non-idealities and signal path mismatches on the differential integrator are investigated. A 5th-order Chebyshev low-pass filter which can be tuned from 1 to 45 MHz is designed. The validity and stability of the proposed circuits are verified using HSPICE simulations.
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  • 6
    Electronic Resource
    Electronic Resource
    Springer
    Analog integrated circuits and signal processing 25 (2000), S. 309-318 
    ISSN: 1573-1979
    Keywords: CMOS ; matching ; micro-loading-effect ; fluctuation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Layout has strong influence on matching properties of a circuit. Current matching models, which characterize both local random non-uniformities and global systematic non-uniformities stochastically, are not adequate for the matching analysis taking the effect of layout realization into account. In order to consider topological information of layout into matching analysis, we propose a matching model which treats the random and systematic components separately. Also, we characterize the micro-loading effect, which modulates fabricated line-width according to the local density of layout patterns, into matching analysis. With these two techniques, we can perform matching analysis of CMOS circuits taking layout information into account.
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  • 7
    Electronic Resource
    Electronic Resource
    Springer
    Analog integrated circuits and signal processing 24 (2000), S. 123-128 
    ISSN: 1573-1979
    Keywords: transconductor ; low-voltage ; CMOS
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A novel voltage-tunable, low-voltage linear CMOS transconductor design is described. The design is based on the improvement of the cross-coupled pairs. SPICE simulation results show that using BSIM models, MOSIS 2-μm n-well process parameters and a power supply of ±2.5 V, the linearity error is less than 0.4% over a differential input voltage range of ±1.2 V. The THD for a differential input voltage of 1V pp at 1 kHz is 1.3%.
    Type of Medium: Electronic Resource
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  • 8
    Electronic Resource
    Electronic Resource
    Springer
    Analog integrated circuits and signal processing 25 (2000), S. 5-15 
    ISSN: 1573-1979
    Keywords: CMOS ; radio frequency ; cell library
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract There is increasing interest in the use of CMOS circuits for high frequency highly integrated wireless telecommunications systems. This paper presents the results of on-going work into the development of a cell library that includes many of the circuit elements required for the high frequency sub-systems of communications integrated circuits. The cell library studied included an RF control element, single ended Class A amplifier, RF isolator, and Gilbert cell mixer circuit topologies. Circuit design criteria and measurement results are presented. All cells were fabricated using standard 2.0, 1.2, and 0.8 μm CMOS integrated circuit fabrication processes with no post-processing performed. The results indicate that 2.0 μm CMOS can be used successfully up to approximately 250 MHz with 0.8 μm cells useful up to approximately 1000 MHz.
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  • 9
    Electronic Resource
    Electronic Resource
    Springer
    Analog integrated circuits and signal processing 25 (2000), S. 347-350 
    ISSN: 1573-1979
    Keywords: analog signal processing ; CMOS ; low voltage ; composite transistor ; multiplier
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to |V t |+2 V ds,sat and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2 μm N-well process with a 3 V supply are given.
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