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  • 1
    ISSN: 1573-1979
    Keywords: transceiver ; CMOS ; front-end ; wireless ; RF
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This work describes the design and realization of a low voltage single-chip wireless transceiver front-end in a standard 0.25 μm CMOS technology. The presented prototype integrates the LNA, down-converters, VCO, quadrature generator, up-converter and pre-amplifier on a single die. A high level of integration is achieved by using a low-IF topology for reception, a direct quadrature up-conversion topology for transmission and an oscillator with on-chip integrated inductor. The final objective of this design is to develop a complete transceiver system for wireless communications at 1.8 GHz that can be built with a minimum of surrounding components: only an antenna, a duplexer, a power amplifier and a baseband signal processing chip. The presented circuit consumes 240 mW from a 2.5 V supply and occupies a die area of 8.6 mm2.
    Type of Medium: Electronic Resource
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  • 2
    Electronic Resource
    Electronic Resource
    Springer
    Analog integrated circuits and signal processing 8 (1995), S. 7-19 
    ISSN: 1573-1979
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract The design and realisation of the analog part for an RDS-receiver, the RDS-detector, is discussed in this paper. The RDS-receiver is developed towards low voltage applications (1.8 V) with low power consumption requirements. A new topology for RDS-receivers is introduced resulting in an important quality improvement, mainly being a higher phase-linearity and a lower power consumption. The performance of the chip is compared to existing RDS-receivers. These receivers use an analog integrated bandpass filter. In the presented topology direct conversion followed by lowpass filtering is used. The chip is realised in a fully differential switched-capacitor technique with correlated double sampling. The latter is used to obtain a very low equivalent input DC-offset. The chip is implemented in a 2µm BiCMOS technology.
    Type of Medium: Electronic Resource
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