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  • fault simulation  (29)
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  • Springer  (35)
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  • 1
    Electronic Resource
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    Springer
    Journal of electronic testing 16 (2000), S. 463-476 
    ISSN: 1573-0727
    Keywords: Delay testing ; design for testability ; fault simulation ; path delay faults ; redundancy removal ; synthesis for testability
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Some false paths are caused by redundant stuck-at faults. Removal of those stuck-at faults automatically eliminates such false paths from the circuit. However, there are other false paths that are not associated with any redundant stuck-at fault. All segments of such a false path are shared with other testable paths. We focus on the elimination of this type of false paths. We use a non-enumerative path delay fault simulator based on the path status graph (PSG) data-structure, which duplicates selected gates to separate the detected and undetected path delay faults. The expanded circuit may contain new redundant stuck-at faults, corresponding to those undetected paths that are false. This happens because the expanded circuit has some new interconnects with only false paths passing through them. Such links become the sites for redundant stuck-at faults. Removal of these redundant faults eliminates false paths. The reported results show that the quality of the result may depend on the coverage of testable paths by the vectors that are simulated. When non-enumerative path delay simulation and implication-based redundancy removal techniques are used, the present procedure of false-path elimination can be applied to very large circuits.
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  • 2
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    Journal of electronic testing 16 (2000), S. 269-278 
    ISSN: 1573-0727
    Keywords: analog testing ; fault simulation ; test optimisation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Analog integrated circuit testing and diagnosis is a very challenging problem. The inaccuracy of measurements, the infinite domain of possible values and the parameter deviations are among the major difficulties. During the process of optimizing production tests, Monte Carlo simulation is often needed due to parameter variations, but because of its expensive computational cost, it becomes the bottleneck of such a process. This paper describes a new technique to reduce the number of simulations required during analog fault simulation. This leads to the optimization of production tests subjected to parameter variations. In Section 1 a review of the state of the art is presented, Section 2 introduces the algorithm and describes the methodology of our approach. The results on CMOS 2-stage opamp and Fifth-order Low-pass switched-capacitor Filter are given in Sections 3 and conclusions in Section 4.
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  • 3
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    Journal of electronic testing 16 (2000), S. 279-288 
    ISSN: 1573-0727
    Keywords: MEMS ; defects ; failure modes ; fault modeling ; HDLs ; fault simulation ; nodal simulation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract As stable fabrication processes for MicroElectroMechanical Systems (MEMS) emerge, research efforts shift towards the design of systems of increasing complexity. The ways in which testing is going to be performed for large volume complex devices embedding MEMS are not known. As in the microelectronics industry, the development of cost-effective tests for larger systems may well require test stimuli targeting actual faults, developing fault lists and fault models for realistic manufacturing defects and failure modes, and using fault simulation as a major approach for assessing testability and dependability. In this paper, we illustrate how fault-based testing can be extended to MEMS, both for bulk and surface micromachining technologies, making possible the reuse of analog testing techniques.
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  • 4
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    Journal of electronic testing 16 (2000), S. 521-539 
    ISSN: 1573-0727
    Keywords: fault simulation ; compaction ; fault diagnosis ; vector restoration ; validation and refinement
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Given a test sequence and a list of faults detected by the sequence, vector restoration techniques extract a minimal subsequence that detects a chosen subset of modeled faults. Vector restoration techniques are useful in static compaction of test sequences and in fault diagnosis. We propose a new vector restoration technique that is a significant improvement over the state of the art in several ways: (1) a sequence of length n can be restored with only O(n log 2 n) simulations while known approaches require simulation of O(n 2) vectors, (2) a two-step restoration process is used that makes vector restoration practical for large designs, and (3) restoration process for several faults is overlapped to provide significant acceleration in vector restoration. Our new ideas can be used to improve run-times of known static compaction and fault diagnosis methods. We integrated the proposed vector restoration technique into a static test sequence compaction system. Our experiments show that the new restoration technique, as compared to known techniques (Proceedings of Int. Conf. on Computer Design, University of Iowa, Aug. 1997, pp. 360–365.), is (1) about 2 times faster for the ISCAS benchmark circuits, and (2) 3 to 5 times faster on large, industrial designs. Using the new restoration technique, we successfully processed large industrial designs that could not be handled by earlier techniques (Proceedings of Int. Conf. on Computer Design, University of Iowa, Aug. 1997, pp. 360–365.) in 2 CPU days.
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  • 5
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    Journal of electronic testing 16 (2000), S. 575-589 
    ISSN: 1573-0727
    Keywords: design validation ; error modeling ; fault simulation ; logic design ; test generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract We investigate an automated design validation scheme for gate-level combinational and sequential circuits that borrows methods from simulation and test generation for physical faults, and verifies a circuit with respect to a modeled set of design errors. The error models used in prior research are examined and reduced to five types: gate substitution errors (GSEs), gate count errors (GCEs), input count errors (ICEs), wrong input errors (WIEs), and latch count errors (LCEs). Conditions are derived for a gate to be testable for GSEs, which lead to small, complete test sets for GSEs; near-minimal test sets are also derived for GCEs. We analyze undetectability in design errors and relate it to single stuck-line (SSL) redundancy. We show how to map all the foregoing error types into SSL faults, and describe an extensive set of experiments to evaluate the proposed method. These experiments demonstrate that high coverage of the modeled errors can be achieved with small test sets obtained with standard test generation and simulation tools for physical faults.
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  • 6
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    Journal of applied electrochemistry 29 (1999), S. 81-85 
    ISSN: 1572-8838
    Keywords: cupric oxide ; powder ; current density ; temperature ; sodium sulfate
    Source: Springer Online Journal Archives 1860-2000
    Topics: Chemistry and Pharmacology , Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Electrosynthesis of cupric oxide powder was carried out on a laboratory scale in an electrochemical cell under various experimental conditions. The electrolysis was appraised in terms of the particle size of the cupric oxide product and the anodic dissolution of the copper electrode. Using a previously determined pH value of 7.50, the other optimum electrolysis operating conditions established were a current density of 4000Am−2, temperature of 353K, and Na2SO4 concentration of 0.5m. The optimum values of current efficiency, cell voltage and specific energy consumption for the electrochemical synthesis of cupric oxide powder were determined.
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  • 7
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    Journal of applied electrochemistry 29 (1999), S. 525-528 
    ISSN: 1572-8838
    Keywords: brine ; chlor-alkali cells ; solubility ; sulfate ions ; temperature
    Source: Springer Online Journal Archives 1860-2000
    Topics: Chemistry and Pharmacology , Electrical Engineering, Measurement and Control Technology
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  • 8
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    Journal of electronic testing 15 (1999), S. 239-254 
    ISSN: 1573-0727
    Keywords: fault coverage estimation ; fault simulation ; test generation ; tolerance ; hyperactivity reduction
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract We present fast, dynamic fault coverage estimation techniques for sequential circuits that achieve high degrees of accuracy and significant reductions in the number of injected faults and faulty-event evaluations. In the proposed techniques, we dynamically reduce injection of hyperactive faults as well as faults whose effects never propagate to a flip-flop or primary output. Suppression and over-specification of potential fault-effects are also investigated to reduce faulty-event evaluations. Experiments show that our methods give very accurate estimates with frequently greater speedups than the sampling techniques for most circuits. Most significantly, the proposed techniques can be combined with the sampling approach to obtain speedups comparable to small sample sizes and retain estimation accuracy of large fault samples.
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  • 9
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    Journal of electronic testing 15 (1999), S. 219-238 
    ISSN: 1573-0727
    Keywords: fault simulation ; symbolic simulation ; SOT ; MOT ; BDD
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract We present a fault simulator for synchronous sequential circuits that combines the efficiency of three-valued logic simulation with the exactness of a symbolic approach. The simulator is hybrid in the sense that three different modes of operation—three-valued, symbolic and mixed—are supported. We demonstrate how an automatic switching between the modes depending on the computational resources and the properties of the circuit under test can be realized, thus trading off time/space for accuracy of the computation. Furthermore, besides the usual Single Observation Time Test Strategy (SOT) for the evaluation of the fault coverage, the simulator supports evaluation according to the more general Multiple Observation Time Test Strategy (MOT). Numerous experiments are given to demonstrate the feasibility and efficiency of our approach. In particular, it is shown that, at the expense of a reasonable time penalty, the exactness of the fault coverage computation can be improved even for the largest benchmark functions.
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  • 10
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    Journal of electronic testing 14 (1999), S. 49-55 
    ISSN: 1573-0727
    Keywords: ATPG ; fault simulation ; fault modelling
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Most industrial digital circuits contain three-state elements besides pure logic gates. This paper presents a gate delay fault simulator for combinational circuits that can handle three-state elements like bus drivers, transmission gates and pulled busses. The well known delay faults--“slow-to-rise” and “slow-to-fall”--are considered as well as delayed transitions from isolating signal state “high impedance” to binary states ‘0’ and ‘1’ and vice versa. The presented parallel delay fault simulator distinguishes between non-robust, robust and hazard free tests and determines the quality of a test. Experimental results for ISCAS85/89 benchmark circuits are presented as well as results for industrial circuits containing three-state elements.
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  • 11
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    Analog integrated circuits and signal processing 16 (1998), S. 141-155 
    ISSN: 1573-1979
    Keywords: analog simulation ; analog test ; fault simulation ; fault modeling ; analog VHDL
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Fault simulation is an accepted part of the test generation procedure for digital circuits. With complex analog and mixed-signal integrated circuits, such techniques must now be extended. Analog simulation is slow and fault simulation can be prohibitively expensive because of the large number of potential faults. We describe how the number of faults to be simulated in an analog circuit can be reduced by fault collapsing, and how the simulation time can be reduced by behavioral modeling of fault-free and faulty circuit blocks. These behavioral models can be implemented in SPICE or in VHDL-AMS and we discuss the merits of each approach. VHDL-AMS does potentially offer advantages in tackling this problem, but there are a number of computational difficulties to be overcome.
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  • 12
    ISSN: 1573-0727
    Keywords: delay test ; fault simulation ; path-delay faults ; transition faults ; statistical fault analysis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract We present a technique to statistically estimate path-delay fault coverage for synchronous sequential circuits. We perform fault-free simulation using a multivalue algebra and accumulate signal transition statistics, from which we calculate controllabilities of all signals and sensitization probabilities for all gates and flip-flops. We use a rated clock testing model where all time frames operate at the rated clock. We obtain path observabilities either by enumerating paths in the all-paths method, or by a nonenumerative method considering only the longest paths. The path-delay fault detectability is the product of observabilities of signals on paths from primary inputs (PIs) or pseudo-primary inputs (PPIs) to primary outputs (POs) or pseudo-primary outputs (PPOs), and the controllability on the corresponding PI or PPI. We use the optimistic update rule of Bose et al. for updating latches during logic simulation. When compared with exact fault simulation, the average absolute deviation in our statistical fault coverage estimation technique is 1.23% and the very worst absolute deviation was 6.59%. On average, our method accelerates delay fault coverage computation four times over an exact path delay fault simulator.
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  • 13
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    Journal of electronic testing 13 (1998), S. 315-319 
    ISSN: 1573-0727
    Keywords: cell fault model (CFM) ; stuck-at fault model ; fault simulation ; test pattern generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Cell Fault Model (CFM) is a well-adopted functional fault model used for cell-based circuits. Despite of the wide adoption of CFM, no test tool is available for the estimation of CFM testability. The vast majority of test tools are based on the single stuck-at fault model. In this paper we introduce a method to calculate the CFM testability of a cell-based circuit using any single stuck-at fault based test tool. Cells are substituted by equivalent cells and Test Generation and Fault Simulation for CFM are emulated by Test Generation and Fault Simulation for a set of single stuck-at faults of the equivalent cells. The equivalent cell is constructed from the original cell with a simple procedure, with no need of knowledge of gate-level implementation, or its function. With the proposed methodology, the maturity and effectiveness of stuck-at fault based tools is used in testing of digital circuits, with respect to Cell Fault Model, without developing new tools.
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  • 14
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    Journal of electronic testing 13 (1998), S. 7-17 
    ISSN: 1573-0727
    Keywords: analog test ; fault modeling ; fault simulation ; noise ; jitter ; behavioral fault modeling
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract It is important to predict noise at the early stages of a top-down design. In this paper, we propose a methodology to model phase noise or jitter, a key specification for phase-locked loops, using a mixed-signal hardware description language, and to simulate the effects of catastrophic faults on the phase jitter at the behavioral level. In contrast to existing approaches which either require dedicated noise simulators or postpone noise and fault simulation to the transistor level, we have successfully demonstrated that noise in a voltage-controlled oscillator (VCO), power supply noise, and their effects on the overall phase jitter within a faulty PLL can be modeled and simulated earlier on at the behavioral level. Our simulation results are consistent with experimentally-verified theoretical predictions.
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  • 15
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    Journal of applied electrochemistry 27 (1997), S. 1328-1332 
    ISSN: 1572-8838
    Keywords: metal hydride ; capacity ; temperature ; performance ; enthalpy
    Source: Springer Online Journal Archives 1860-2000
    Topics: Chemistry and Pharmacology , Electrical Engineering, Measurement and Control Technology
    Notes: Abstract The effect of temperature on the performance of a LaNi4.76Sn0.24 metal hydride electrode was investigated in the temperature range of 0 to 50°C. The electrode showed a maximum discharge capacity at 25°C. The total resistance increases with a decrease of temperature from 50°C to 0°C. The apparent activation enthalpies at different states of charge were determined by evaluating the polarization resistance at different temperatures. It was found that the apparent activation enthalpy is an indicator of the relative reaction rate of the charge-transfer reaction and hydrogen absorption.
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  • 16
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    Journal of nondestructive evaluation 16 (1997), S. 91-100 
    ISSN: 1573-4862
    Keywords: LASER ultrasound ; anisotropic material ; group velocity ; stiffness coefficients ; temperature
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology , Mathematics
    Notes: Abstract Ultrasonic waves are generated through a composite material by means of a noncontact technique. It uses a Nd:Yag LASER for the generation and an interferometric probe for the detection of acoustic waveforms. From a suitable set of experimental data, an inversion scheme is used for the recovering of four stiffness coefficients. They characterize the elasticity in a principal plane of symmetry of the material which exhibits an orthorhombic symmetry. The measurements are performed at various temperatures, elevated by steps up to 300°C for two specimen. The sensitivity of the method appears convenient to measure the temperature induced stiffness changes. The anisotropic degradation of the material properties are then pointed out.
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  • 17
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    Journal of electronic testing 10 (1997), S. 271-276 
    ISSN: 1573-0727
    Keywords: fault simulation ; bridging faults ; binary decision diagrams (BDDs)
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper introduces a new fault simulation methodology based onsymbolic handling of fault effects. Boolean variables are related tofaulty signals, and fault effects are propagated by computing gateoutput expressions by means of BDDs. The proposed technique canhandle in a single simulation step such faults as resistive bridges,that exhibit a parametric behavior, thus requiring more simulationswith conventional techniques.
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  • 18
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    Journal of electronic testing 10 (1997), S. 277-282 
    ISSN: 1573-0727
    Keywords: fault simulation ; logic simulation ; parallel simulation ; parallelization ; workload distribution
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Simulation at the gate level is computationally very expensive.Parallel processing is one technique to reduce simulation time.Possessing knowledge of the distribution of computational activity insimulation can aid in parallelizing it efficiently. We present a newcharacterization of the distribution of the computational workload infault simulation. An empirical analysis shows that the workloaddistribution is circuit specific, and is largely independent of thevector set being simulated. An inexpensive method to predict theworkload distribution is also discussed.
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  • 19
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    Analog integrated circuits and signal processing 14 (1997), S. 193-206 
    ISSN: 1573-1979
    Keywords: sensor interface ; accelerometer ; temperature ; telemetry ; biomedical implants
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper describes the development of two small dataacquisition chips with on board interface circuits for a miniaturisedcapacitive accelerometer, as well as for a set of thermistors.They are intended for use in biomedical, implantable telemetryapplication, requiring low power and small size for the entiresystem. Beside the typical aspects of circuit design, emphasisis also put on the overall system design, to pinpoint to thetypical constraints of the application. This leads to one ofits most important features: the flexible specifications, allowinga user-defined setting of the monitoring windows, after the deviceis manufactured. In the paper this concept is explained, andan example of a hard-wired system and a software controlled systemare given.
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  • 20
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    Journal of electronic testing 8 (1996), S. 143-152 
    ISSN: 1573-0727
    Keywords: fault simulation ; mixed-signal systems ; bridging faults
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper proposes a solution to achieve the global fault simulation for mixed-signal systems. Fault models for analog defects are introduced. Short-circuit defects, involving two digital nodes or involving a digital and an analog node, are also supported. Short-circuit modelling is achieved by a local analog simulation and by means of new mixed-signal models suggested for CMOS devices. Using a commercially available mixed-signal simulator, we built surrounding tools to automate the fault simulation. By processing the circuit description files, they allow generating and reducing a fault list and controlling the fault simulation, Simulation results are also processed in order to produce an exhaustivity report and a selection of the best test vectors.
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  • 21
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    Journal of electronic testing 9 (1996), S. 29-41 
    ISSN: 1573-0727
    Keywords: testing ; mixed-signal ; fault simulation ; arithmetic distance
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract The rapidly evolving role of analog signal processing has spawned off a variety of mixed-signal circuit applications. The integration of the analog and digital circuits has created a lot of concerns in testing these devices. This paper presents an efficient unified fault simulation platform for mixed-signal circuits while accounting for the imprecision in analog signals. While the classical stuck-at fault model is used for the digital part, faults in the analog circuit cover catastrophic as well as parametric defects in the passive and active components. A unified framework is achieved by combining a discretized representation of the analog circuit with the Z-domain representation of the digital part. Due to the imprecise nature of analog signals, an arithmetic distance based fault detection criterion and a statistical measure of digital fault coverage are proposed.
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  • 22
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    Journal of electronic testing 9 (1996), S. 267-277 
    ISSN: 1573-0727
    Keywords: logic simulation ; fault simulation ; parallel sequence simulation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A novel parallel sequence fault simulation (PSF) algorithm for synchronous sequential circuits is presented. The algorithm successfully extend the parallel pattern method for combinational circuits to sequential circuits by proposing a multiple-pass mechanism to overcome the state dependency in sequential circuits. The fault simulation is performed in parallel by partitioning the entire sequence into subsequences of equal length. Furthermore, techniques are developed to minimize the number of simulation passes. Notably, two compact counters, C x and C d , are proposed to faciliate the early stabilization detection of faulty circuit simulation with minimum space overhead. The experimental results on the benchmark circuits show that the speedup ratio over a serial sequence fault simulator based on ROOFS is 9.16 on average for pseudo random vectors. The parallel sequence algorithm of PSF is especially adaptable to parallel and distributed simulation which exploits sequence partition.
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  • 23
    ISSN: 1573-0727
    Keywords: Built-in self-test ; compact testing ; fault coverage ; fault simulation ; signature analysis ; multiple signature analysis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract In this article, a strategy based on the use of intermediate signatures is proposed that enables the exact fault coverage of compact testing schemes to be determined in a feasible computation time. Two models to predict fault simulation time, a fault simulator dependent and independent model, are developed and used by a dynamic programming based algorithm to find the optimal scheduling of the signatures with respect to the total simulation time. Simulation results for both models are then presented demonstrating the feasibility of the proposed strategy.
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  • 24
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    Natural hazards 9 (1994), S. 5-16 
    ISSN: 1573-0840
    Keywords: Fourier transform ; maximum entropy spectral analysis ; precipitation ; temperature ; climatic change
    Source: Springer Online Journal Archives 1860-2000
    Topics: Energy, Environment Protection, Nuclear Power Engineering , Geography , Geosciences
    Notes: Abstract In the present work, a precipitation and temperature series from Barcelona (Spain) are analysed in order to detect the possible existence of climatic changes or cycles. The analysis is carried out both from the temporal and spectral standpoints. The techniques used range from the classical periodogram and Blackman-Tukey method through to the Maximum Entropy method. The results do not show the existence of climatic cycles, though they do show a clear tendency toward increased precipitation and decreased temperature, since the last years of series.
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  • 25
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    Journal of electronic testing 4 (1993), S. 131-135 
    ISSN: 1573-0727
    Keywords: Gate delay fault ; fault simulation ; robust test ; sequential circuit
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This article proposes a 7-valued logic appropriate for test generation and fault simulation, in the area of robust tests for gate delay faults, and a straightforward simulation strategy for sequential circuits. It is shown that a purely qualitative logic of robust testing is inadequate for circuits with edge-triggered flip-flops. The relation between the 7-valued logic and the similar logic proposed before by Smith, Schulz et al., and Lin and Reddy are discussed.
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  • 26
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    Journal of electronic testing 4 (1993), S. 255-265 
    ISSN: 1573-0727
    Keywords: Critical path tracing ; fault simulation ; parallel pattern simulation ; single fault propagation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract We present a fast fault simulation algorithm for combinational circuits which combines parallel pattern evaluation and critical path tracing. When the number of faults is large, our algorithm exploits the full advantages of critical path tracing. As fault dropping progresses, the overhead for critical path tracing surpasses its advantages. On the other hand, the efficiency of Parallel Pattern Single Fault Propagation (PPSFP) increases rapidly since relatively few undetected faults remain, and they tend to be inactive. To avoid the overhead of critical path tracing and achieve the advantages of PPSFP, dynamic update of node classes is used to produce a smooth transition from critical path tracing to PPSFP. By using this approach, we get high performance for both small and large numbers of test patterns. Also, preprocessing related to structure analysis is avoided while achieving almost all of its advantages.
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  • 27
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    Journal of electronic testing 3 (1992), S. 197-205 
    ISSN: 1573-0727
    Keywords: Bridging faults ; fault models ; fault simulation ; test invalidation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Dynamic effects in the detection of bridging faults in CMOS circuits are taken into account showing that a test vector designed to detect a bridging may be invalidated because of the increased propagation delay of the faulty signal. To overcome this problem, it is shown that a sequence of two test vectors 〈 T 0, T 1 〉, in which the second can detect a bridging fault as a steady error, can detect the fault independently of additional propagation delays if T0 initializes the faulty signal to a logic value different from the fault-free one produced by T 1. This technique can be conveniently used both in test generation and fault simulation. In addition, it is shown how any fault simulator able to deal with FCMOS circuits can be modified to evaluate the impact of test invalidation on the fault coverage of bridging faults. For any test vector, this can be done by checking the state of the circuit produced by the previous test vector.
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  • 28
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    Journal of electronic testing 2 (1991), S. 181-190 
    ISSN: 1573-0727
    Keywords: bridging faults ; CMOS circuits ; critical path analysis ; fault simulation ; stuck-open faults
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This work presents a technique to correctly deal with non-stuck-at faults in FCMOS circuits making use of complex macrogates. This method can be applied to any gate-level fault simulator providing, for each line of the circuit, the observability status that is directly related to that of individual devices in the actual macrogate implementation. Conductance conflicts are correctly solved to detect bridgings and transistors stuck-on. Fault coverage results are presented and discussed for two typical FCMOS circuits. Results obtained on all ISCAS benchmarks show that the time required for the fault simulation of CMOS faults is comparable to that of stuck-ats.
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  • 29
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    Journal of electronic testing 2 (1991), S. 135-151 
    ISSN: 1573-0727
    Keywords: behavior model ; fault coverage correlation ; fault model ; fault simulation ; stuck-at fault
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A critical aspect of digital electronics is the testing of the manufactured designs for correct functionality. The testing process consists of first generating a set of test vectors, then applying them as stimuli to the manufactured designs, and finally comparing the output response with that of the desired response. A design is considered acceptable when the output response matches the desired response and is rejected otherwise. Fundamental to the process of test vector generation is the assumption of an underlying fault model that is a model of the failures introduced during manufacture. The choice of the fault model influences the accuracy of testing and the computer CPU time required to generate test vectors for a given design. The most popular fault model in the industry today is the single stuck-at fault at the gate level that requires exorbitantly large CPU times for moderately complex digital designs. This article introduces new high-level behavior fault models that are associated with high-level hardware descriptions of digital designs. The derivation of these faults is based on the failure modes of the language constructs of the high-level hardware description language. Behavior faults include multiple input stuck-at faults and this article also reasons the nature of test vectors for such faults. The potential advantages of behavior fault modeling include early estimates of fault coverage in the design process prior to the synthesis of the gate-level representation of the design, faster fault simulation, and results that may be more comprehensible to the high-level architects. The behavior-fault-modeling approach is evaluated through a study of correlation of the results of behavior fault simulation of several representative digital designs with the results of gate-level single stuck-at fault simulation of equivalent gate-level representations.
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  • 30
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    Journal of electronic testing 2 (1991), S. 191-203 
    ISSN: 1573-0727
    Keywords: Bayesian estimation ; confidence level ; fault simulation ; sampling
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This article emphasizes simulation-based sampling techniques for estimating fault coverage that use small fault samples. Although random testing is considered to be the primary area of application of the technique it is also suitable for estimating the fault coverage of nonrandom tests based on specific fault models. Especially for fault coverages exceeding 95%, it is shown that a precise estimate can be obtained using a fault sample of only 500 faults. The estimation is based on a binomial approximation of the probability density of the sample fault coverage. Using Bayes statistics an estimate is obtained whose accuracy is a linear function of the sample size if the fault coverage approaches 100%. The sample size is independent of the circuit size, thus making fault sampling particularly interesting for the fault simulation of ULSI designs due to the resulting reduction of the time complexity of fault simulation from O(N 2) to O(N).
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  • 31
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    Journal of electronic testing 1 (1991), S. 275-286 
    ISSN: 1573-0727
    Keywords: fault simulation ; robust tests ; stuck-open faults ; test generation algorithms
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Tests for stuck-open faults in static CMOS circuits consist of a sequence of two input vectors. Such test-pairs may be invalidated by delays in the circuit. Test-pairs that are not invalidated by delays in the circuit are known as robust test-pairs. We present a six-valued logic system Ω = {0, 1, r, f, 0h, 1h}. We show how Ω differs from a number of other logic systems that have been proposed for test generation. This logic system abstracts the important aspects of the transition behavior of the circuit, on application of an input pair, that is necessary to characterize robust test-pairs for stuck-open faults. This characterization of robust test-pairs is used to derive: (i) an algorithm for determining if a given test-pair is a robust test-pair for a given stuck-open fault or not; and (ii) a simplified algorithm for computing a robust test-pair for a stuck-open fault. The resulting algorithm for computing robust tests for stuck-open faults can be implemented by minor modifications to test generation algorithms for stuck-at faults.
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  • 32
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    Journal of electronic testing 1 (1990), S. 7-13 
    ISSN: 1573-0727
    Keywords: fault simulation ; sequential circuits ; test generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A new fast fault simulation algorithm called differential fault simulation, DSIM, for synchronous sequential circuits is described. Unlike concurrent fault simulation, for every test vector, DSIM simulates the good machine and each faulty machine separately, one after another, rather than simultaneously simulating all machines. Therefore, DSIM dramatically reduces the memory requirement and the overhead in the memory management in concurrent fault simulation. Also, unlike serial fault simulation, DSIM simulates each machine by reprocessing its differences from the previously simulated machine. In this manner, DSIM is more efficient than serial fault simulation. Experiments have shown that DSIM runs 3 to 12 times faster than an existing concurrent fault simulator. In addition, owing to the simplicity of this algorithm, DSIM is very easy to implement and maintain. An implementation consists of only about 300 lines of “C” language statements added to the event-driven true-value simulator in an existing sequential circuit test generator program, STG3. Currently DSIM uses the zero-delay timing model. The addition of alternative delay models is under development.
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  • 33
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    Journal of electronic testing 1 (1990), S. 139-149 
    ISSN: 1573-0727
    Keywords: fault simulation ; multilevel simulation ; testing ; VLSI design
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This article discusses an approach for hierarchical multilevel fault simulation for large systems described at the transistor, gate, and higher levels. The approach reduces the memory requirement of the simulation drastically, thus allowing the simulation of circuits that are too large to simulate at one flat level on typical engineering workstations. This is achieved by exploiting the regularity and modularity found in a hierarchical circuit description that contains many repeated substructures. The hierarchical setup also allows flexible multilevel simulation: behavioral models can replace subcircuits at any level of the hierarchy for accelerated simulation. The simulation algorithms are at the switch level so that general MOS digital designs with bidirectional signal flow can be handled, and both stuck-at and transistor faults are treated accurately. The approach has been implemented in the hierarchical logic and fault simulation system, CHAMP, that runs under UNIX on SUN-3 and SUN-4 workstations. It has been used successfully for simulating and fault grading a large commercial microprocessor.
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  • 34
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    Journal of electronic testing 1 (1990), S. 183-189 
    ISSN: 1573-0727
    Keywords: D-algorithm ; fault simulation ; fault target switching
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract We describe an extended selection of switching target faults in the CONT algorithm. The main difficulty in test generation is the conflict that arises in the process of determining the signal values due to reconvergent fanouts. Conventional approaches for test generation change a signal value, which causes conflicts to another possible choice for backtracking. In the CONT algorithm, a strategy of switching target fault was proposed as a new backtracking mechanism. In this method, the target fault is switched to a new target fault instead of making an alternative assignment on the primary input value when a conflict occurs. A disadvantage of the CONT algorithm is that unjustified lines exist in the process of test generation. These unjustified lines make the procedure of switching targets complicated and restrict the possible choice in selecting the new target fault. In the new version of CONT, called CONT-2, we have removed the unjustified lines in the process of test generation and have extended to two target-fault types for switching targets. Implementing CONT-2 by a Fortran program, ISCAS85 benchmark circuits are examined. Experiments on a combined system with fault simulation followed by CONT-2 are also presented.
    Type of Medium: Electronic Resource
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  • 35
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 1 (1990), S. 183-189 
    ISSN: 1573-0727
    Keywords: D-algorithm ; fault simulation ; fault target switching
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract We describe an extended selection of switching target faults in the CONT algorithm. The main difficulty in test generation is the conflict that arises in the process of determining the signal values due to reconvergent fanouts. Conventional approaches for test generation change a signal value, which causes conflicts to another possible choice for backtracking. In the CONT algorithm, a strategy of switching target fault was proposed as a new backtracking mechanism. In this method, the target fault is switched to a new target fault instead of making an alternative assignment on the primary input value when a conflict occurs. A disadvantage of the CONT algorithm is that unjustified lines exist in the process of test generation. These unjustified lines make the procedure of switching targets complicated and restrict the possible choice in selecting the new target fault. In the new version of CONT, called CONT-2, we have removed the unjustified lines in the process of test generation and have extended to two target-fault types for switching targets. Implementing CONT-2 by a Fortran program, ISCAS85 benchmark circuits are examined. Experiments on a combined system with fault simulation followed by CONT-2 are also presented.
    Type of Medium: Electronic Resource
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