ALBERT

All Library Books, journals and Electronic Records Telegrafenberg

Your email was sent successfully. Check your inbox.

An error occurred while sending the email. Please try again.

Proceed reservation?

Export
Filter
  • Articles  (27)
  • Data
  • built-in self-test  (27)
  • Springer  (27)
  • Molecular Diversity Preservation International
  • Electrical Engineering, Measurement and Control Technology  (27)
Collection
  • Articles  (27)
  • Data
Publisher
  • Springer  (27)
  • Molecular Diversity Preservation International
Years
Topic
  • Electrical Engineering, Measurement and Control Technology  (27)
  • 1
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 8 (1996), S. 153-164 
    ISSN: 1573-0727
    Keywords: cellular automata ; test vector generator ; built-in self-test ; rank order clustering
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper proposes a new approach to designing a BIST Test Vector Generator (TVG) for random vector-resistant circuits based on reconfigurable Cellular Automata Registers (CARs). Each CAR configuration is constructed by combining rules 90 and 150 and the same approach can also be applied to the Linear Feedback Shift Register (LFSR). The TVG thus designed is able to produce 100% fault coverage with short test time at the cost of low area overhead. To achieve this objective, a new method called the Rank Order Clustering (ROC) method, is introduced in order to fix a number of inputs at certain values when generating pseudorandom vectors. It is shown that the ROC method is very simple and efficient in fixing inputs at these values in terms of complexity. Experimental results have been conducted to demonstrate the applicability of the proposed approach in terms of hardware size and test application time.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 2
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 7 (1995), S. 125-137 
    ISSN: 1573-0727
    Keywords: built-in self-test ; design for testability ; partial scan ; test points
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Partial-Scan based Built-In Self-Test (PSBIST) is a versatile Design for Testability (DFT) scheme, which employs pseudo-random BIST at all levels of test to achieve fault coverages greater than 98% on average, and supports deterministic partial scan at the IC level to achieve nearly 100% fault coverage. PSBIST builds its BIST capability on top a partial scan structure by adding a test pattern generator, an output data compactor, and a PSBIST controller in a way similar to that of deriving a full scan BIST from a full scan structure. However, to make the scheme effective, there is a minimum requirement regarding which flip-flops in the circuit should be replaced by scan flip-flops and/or initialization flip-flops. In addition, test arents are usually added to boost the fault coverage to the range of 95 to 100 percent. These test points are selected based on a novel probabilistic testability measure, which can be computed extremely fast for a special class of circuits. This ciass of circuits is precisely the type of circuits that we obtain after replacing some of the flip-flops.withscan and/or initilization flip-flops. The testability measure is also used for a very useful quick estimation of the fault coverage right after the selection of sean flip-flops, even before the circuit is modified to incorporate PSBIST capability. While PSBIST provides all the benefits of BIST, it incurs lower area overhead and performance degradation than full scan. The area overhead is further reduced when the boundary scan cells are reconfigured for BIST usage.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 3
    ISSN: 1573-0727
    Keywords: built-in self-test ; linear feedback shift register ; linear finite state machine ; linear hybrid cellular automata ; sequential fault ; transition capability
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper presents a combinatorial method of evaluating the effectiveness of linear hybrid cellular automata (LHCA) and linear feedback shift registers (LFSR) as generators for stimulating faults requiring a pair of vectors. We provide a theoretical analysis and empirical comparisons to see why the LHCA are better than the LFSRs as generators for sequential-type faults in a built-in self-test environment. Based on the concept of a partner set, the method derives the number of distinctk-cell substate vectors which have 22k , 1≤k≤[n/2], transition capability for ann-cell LHCA and ann-cell LFSR with maximum length cycles. Simulation studies of the ISCAS85 benchmark circuits provide evidence of the effectiveness of the theoretrical metric.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 4
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 6 (1995), S. 139-140 
    ISSN: 1573-0727
    Keywords: Aliasing ; built-in self-test ; error models ; signature analysis ; test response compaction
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract The analysis of aliasing probability presented in a recent article, “Aliasing Properties of Circular MISRs” [1], is based on an error model that cannot adequately represent real circuits. We show why conclusions presented in [1] should not be used in practice, substantiating our claim with experimental results.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 5
    Electronic Resource
    Electronic Resource
    Springer
    Analog integrated circuits and signal processing 12 (1997), S. 29-48 
    ISSN: 1573-1979
    Keywords: high frequency multiplexer/demultiplexer circuits ; built-in self-test
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Full functional test at speed, in-situ is an ideal choice for use for detection of errors in circuit behaviour for high speed broadband communication circuits and to avoid test set-up disturbances on high frequency signals. This article presents a novel technique to solve the high frequency test of Gbit/s data rate Time-Division Multiplexer/Demultiplexer circuits. This in-situ test technique is based on conventional pseudo-random sequence generation and signature analysis. By linear feedback interconnect and reusable architecture the multiplexer/demultiplexer circuits can operate as generator/analyser with minimal degeneration of bit shift rate. Circuit simulation showed that the system operates correctly with a clock frequency up to 3 GHz in a silicon bipolar technology with a current gain cut-off frequency f T = 15 GHz.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 6
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 12 (1998), S. 111-125 
    ISSN: 1573-0727
    Keywords: built-in self-test ; carry lookahead ; datapath circuits ; on-line testing ; scalability ; test generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper explores the design of efficient test sets and test-pattern generators for on-line BIST. The target applications are high-performance, scalable datapath circuits for which fast and complete fault coverage is required. Because of the presence of carry-lookahead, most existing BIST methods are unsuitable for these applications. High-level models are used to identify potential test sets for a small version of the circuit to be tested. Then a regular test set is extracted and a test generator TG is designed to meet the following goals: scalability, small test set size, full fault coverage, and very low hardware overhead. TG takes the form of a twisted ring counter with a small decoder array. We apply our technique to various datapath circuits including a carry-lookahead adder, an arithmetic-logic unit, and a multiplier-adder.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 7
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 12 (1998), S. 139-144 
    ISSN: 1573-0727
    Keywords: built-in self-test ; off-line testing ; non-volatile memories ; signature analysis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A new BIST scheme for on-chip testing of non-volatile memories and based on signature analysis is presented. The signature of the whole memory, whose content can be changed selectively by the user, is dynamically self-learned by the memory and it is saved in a dedicated memory location. Either such a signature can be externally compared with the expected one in order to check for the programming operation, or it can be used for comparison purposes when data retention must be self-tested.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 8
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 13 (1998), S. 221-237 
    ISSN: 1573-0727
    Keywords: built-in self-test ; high-level synthesis ; estimation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Lower bound estimations of functional resources at various stages of high-level synthesis have been developed to guide synthesis algorithms toward optimal solutions. In this paper we present lower bounds on the number of test resources (i.e., registers that generate pseudo-random test patterns and/or compress test responses) required to test a synthesized data path using built-in self-test (BIST). The bounds on different types of test resources are proved to be individually achievable and experiments show that in most cases the bounds can be achieved simultaneously and with minimum number of functional registers. Efficient ways of computing the lower bounds are developed. The estimations are performed on scheduled data flow graphs with a given module assignment and provide a practical way of selecting or modifying module assignments and schedules such that the resulting synthesized data path requires a small number of BIST resources to test itself.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 9
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 16 (2000), S. 355-367 
    ISSN: 1573-0727
    Keywords: on-line test ; code checkers ; code word accumulators ; code word generators ; embedded checkers ; totally self-checking checkers ; cyclic arithmetic codes ; low-cost arithmetic codes ; built-in self-test
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Code checkers that monitor the outputs of a system can detect both permanent and transient faults. We present two novel architectures of embedded self-testing checkers for low-cost and cyclic arithmetic codes, one based on code word generators and adders, the other based on code word accumulators. In these schemes, the code checker receives all possible code words but one, irrespective of the number of different code words that are produced by the circuit under check (CUC). So any code checker can be employed that is self-testing for all or a particular subset of code words, and the structure of the code checker need not be tailored to the set of code words produced by the CUC. The proposed code word generators and accumulators are built from simple standard hardware structures, counters and end-around-carry adders. They can also be utilized in an off-line BIST environment as pattern generators and test response compactors.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 10
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 16 (2000), S. 419-426 
    ISSN: 1573-0727
    Keywords: built-in self-test ; two-pattern test ; configurable LFSR ; path delay faults
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper proposes an approach to designing a cost-effective deterministic test pattern generator (TPG) for two-pattern testing. Given a set of pre-generated test-pair set (obtained by an ATPG tool) with a pre-determined (path delay) fault coverage, a simple TPG is synthesized to apply the given test-pair set in a minimal test time. To achieve this objective, a configurable linear feedback shift register (CLFSR) structure is used. Techniques are developed to synthesize such a TPG, which is used to generate an unordered deterministic test-pair set. The resulting TPG is efficient in terms of hardware size and speed performance. Experiments on benchmark circuits indicate that TPG designed using the proposed procedure obtain high path delay fault coverage in short test length.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 11
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 3 (1992), S. 149-157 
    ISSN: 1573-0727
    Keywords: built-in self-test ; PLA ; random pattern testability ; testable design
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Programmable Logic Arrays (PLAs) provide a cost effective method to realize combinational logic circuits. PLAs are often not suitable for random pattern testing due to high fao-in of gates. In order to reduce the effective fan-in of gates, previous random pattern testable (RPT) PLA designs focused on partitioning inputs and product lines. In this paper we propose a new random pattern testable design of PLAs which is suitable for built-in selftest. The key idea of the proposed design is to apply weighted random patterns to the PLA under test. The proposed design method was applied to 30 example PLAs. The performance of the RPT PLAs was measured in the size of test set, area overhead, and time overhead, and compared with two other designs in test length and fault coverage. The experimental results show that the proposed design achieve short test length and high fault coverage.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 12
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 1 (1991), S. 301-304 
    ISSN: 1573-0727
    Keywords: built-in self-test ; design for testability ; signature testing
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Here we propose a new approach to the testing of digital devices, which can potentially save diagnostic hardware. An example is given for testing combinational devices. Estimates are given for reliability and hardware complexity, and an algorithm for designing operability tests is described.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 13
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 10 (1997), S. 87-95 
    ISSN: 1573-0727
    Keywords: MCM testing ; built-in self-test ; DFT
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper addresses the general problem of module level test ofassembled Multi-Chip Modules (MCMs) and specifically the performancetest of such modules. It presents a novel solution based-on built-in self-test (BIST). This solutionaugments the conventional single-chip BIST approach, which is used to produce individual good dies, to an effective multi-chip BIST solution. The multi-chip BIST puts the entire module in a self-test mode. The self-test mode not only provides effective detection of static and dynamic faults, but also identifies the failed elements, i.e., bad dies or substrate. The multi-chip self-test scheme is based on pseudo-random test generation and uses multi-signature evaluation. The hardware design ofmulti-chip and single-chip self-test blocks is combined under one common architecture called the Dual BIST Architecture. The paper introduces the Dual BIST Architecture and demonstrates a set of design configurations to implement it. The presented BIST solution provides a reliable static and dynamic test at the module as well as the bare die levels.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 14
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 10 (1997), S. 127-136 
    ISSN: 1573-0727
    Keywords: Multichip Module test and diagnosis ; system diagnosis ; built-in self-test ; signature analysis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A system diagnosis technique for multichip module (MCM) ispresented. The proposed technique uses built-in probes for monitoringinternal responses and, with a signature analysis scheme based onerror correcting codes, identifies the probes where erroneous test responses have been detected. Conceptsfrom system diagnosis is used in conjunction withsignature analysis in developing the proposed MCM diagnosistechnique, where the resulting patterns of the faulty probes are usedin the identification of the faulty submodules (dies). The proposedtechnique offers a diagnostic capability in system functional test.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 15
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 10 (1997), S. 215-229 
    ISSN: 1573-0727
    Keywords: memory testing ; pattern sensitive faults ; built-in self-test ; exhaustive codes ; near-exhaustive codes
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract In this work we investigate the problem of detection and location ofsingle and unlinked multiple k-coupling faults in n × 1 random-access memories (RAMs). This fault model covers allcrosstalks between any k cells in n × 1 RAMs. The problem of memory testing has been reduced to the problem of the generationof (n,k-1)-exhaustive backgrounds. We have obtained practical test lengths, for a memory size around 1 M, for detecting up to6-couplings by exhaustive tests and up to 9-couplings bynear-exhaustive tests. The best known test algorithms up to nowprovide for the detection of 5-couplings only in a 1 M memory, usingexhaustive tests. Beyond these parameters, test lengths wereimpractical. Furthermore, our method for generation of(n,k-1)-exhaustive backgrounds yields short test lengths givingrise to considerably shorter testing times than the present mostefficient tests for large n and for k greater than 3. Our test lengths are 50% shorter than other methods for the case of detectingup to 5-couplings in a 1 Mbit RAM. The systematic nature of both ourtests enables us to use a built-in self-test (BIST) scheme, for RAMs, with low hardware overhead. For a 1Mbit memory, the BIST areaoverhead for the detection of 5-couplings is less than 1% for SRAMand 6.8% for a DRAM. For the detection of 9-couplings with 99% or higher probability, the BIST area overhead is less than 0.2% forSRAM and 1.5% for DRAM.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 16
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 11 (1997), S. 69-80 
    ISSN: 1573-0727
    Keywords: accumulator ; adder ; built-in self-test ; pattern generator ; subtracter
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Configurations of adders, subtracters, or arithmetic logic units andregisters, which are available in many data paths, can be utilized togenerate patterns and to compact test responses. This paper analyzesthe pattern sequences generated by configurations with differenttypes of adders and subtracters. For many different seeds andconstant input values, these pattern generators can produce asequence of all possible patterns. Moreover, k-bit patterngenerators that take into account the overflow or underflow bit cangenerate bit sequences that all have period 2 k -1. Thus, theperiodicity of these pattern generators is the same as that of a k-bit linear feedback shift register with a primitivecharacteristic polynomial. Experimental results show that theproduced pattern sequences achieve similar fault coverage aspseudorandom sequences and require about the same testlength. Compared to the well-known self-test methods that insert testregisters, the approach using available arithmetic units saves theadditional gates that are needed to implement test registers, and itavoids performance degradation due to additional delays.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 17
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 9 (1996), S. 251-266 
    ISSN: 1573-0727
    Keywords: random access memory ; memory testing ; transparent memory testing ; built-in self-test ; pseudoexhaustive memory testing ; pattern sensitive faults ; signature analysis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper presents a new methodology for RAM testing based on the PS(n, k) fault model (the k out of n pattern sensitive fault model). According to this model the contents of any memory cell which belongs to an n-bit memory block, or the ability to change the contents, is influenced by the contents of any k -1 cells from this block. The proposed methodology is a transparent BIST technique, which can be efficiently combined with on-line error detection. This approach preserves the initial contents of the memory after the test and provides for a high fault coverage for traditional fault and error models, as well as for pattern sensitive faults. This paper includes the investigation of testing approaches based on transparent pseudoexhaustive testing and its approximations by deterministic and pseudorandom circular tests. The proposed methodology can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 18
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 12 (1998), S. 171-185 
    ISSN: 1573-0727
    Keywords: MIMD architectures ; routing test ; IEEE 1149.1 ; built-in self-test ; diagnosis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper presents an implementation approach for the test of routers in a fine grain massively parallel architecture. First, an ad hoc test technique which diffuses test messages router by router is analyzed. Even though the technique does not add hardware, it is shown inefficient and not applicable due to practical constraints such as the limited number of pins of the chip implementing the machine. Based on a hierarchical implementation of the IEEE 1149.1 standard, two approaches are proposed and compared in terms of the area overhead, the overall test time and the flexibility in applying tests and diagnosing the routers inside the machine. The basic idea for both approaches is to construct groups of basic cells which are driven by the same test block and compare their test results after the same test vectors are applied at each cell input. The two approaches differ in the granularity of a basic cell. The choice of an implementation approach is not trivial. It is shown that each approach presents better performance than the other, that is, the approach which allows better fault coverage and less test time requires more silicon and less diagnostic possibilities compared to the second approach.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 19
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 13 (1998), S. 273-297 
    ISSN: 1573-0727
    Keywords: test control ; boundary scan ; built-in self-test ; design-for-test ; test bus ; local test control ; distributed test control ; dynamic test control
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper deals with a design methodology and associated architecture to support the control of on-chip DFT and BIST hardware. The work is general in that it supports numerous test methods, such as partial and full scan, multiple and reconfigurable scan chains, and both test per clock BIST and scan BIST. The results presented here are compatible with the IEEE 1149.1 boundary scan architecture. The work is based on a hierarchical control methodology that includes systems, PCBs and MCMs. Various options for assigning control functions to be on-chip or off-chip are described. A new, partially distributed test control architecture is introduced that includes an internal test bus and distributed local controllers. There are three main modes of control of test resources, namely local static control, dynamic control and global static control. We show how the control mechanism can be implemented together with the IEEE 1149.1 test protocol. The synthesis of the on-chip test control hardware has been automated in a system called CONSYST.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 20
    ISSN: 1573-0727
    Keywords: built-in self-test ; embedded cores ; EDA tools
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper presents a High-Level EDA environment based on the Hierarchical Distributed BIST (HD-BIST), a flexible and reusable approach to solve BIST scheduling issues in System-on-Chip applications. HD-BIST allows activating and controlling different BISTed blocks at different levels of hierarchy, with a minimum overhead in terms of area and test time. Besides the hardware layer, the authors present the HD-BIST application layer, where a simple modeling language, and a prototypical EDA tool demonstrate the effectiveness of the automation of the HD-BIST insertion in the test strategy definition of a complex System-on-Chip.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 21
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 16 (2000), S. 185-192 
    ISSN: 1573-0727
    Keywords: pseudorandom testing ; built-in self-test ; testing of cores ; test-ready intellectual property
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract In this paper we show, that the statistical properties of cryptographic algorithms are the reason for the excellent pseudorandom testability of cryptographic processor cores. The work is especially concerned with modern symmetric block encryption algorithms and their VLSI implementations. For the examination typical basic operations of these cryptographic algorithms are categorized in classes and analyzed regarding their pseudorandom properties. Based on the results the pseudorandom properties of symmetric block ciphers can be determined by means of data flow graphs (DFG) and so-called predecessor operation lists. This is demonstrated with a paradigm algorithm, the symmetric block cipher 3WAY. The results of the theoretical analysis lead to a so-called global BIST concept for cryptographic processor cores. This self-test approach is characterized by central pseudorandom pattern generators and signature registers at the primary inputs and outputs of the cores. The global BIST is exemplarily applied to an implementation of the 3WAY algorithm. Finally, the quality of the developed test approach is determined by fault simulations.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 22
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 16 (2000), S. 427-442 
    ISSN: 1573-0727
    Keywords: boundary scan ; built-in self-test ; BIST ; cluster testing ; interconnect testing
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A novel built-in self-test (BIST) architecture and a test pattern generator (TPG) design methodology to program this architecture are presented for inter-IC interconnects among combinational non-boundary scan ICs (often called cluster-ICs) via IEEE 1149.1 boundary scan architecture (BSA). Due to the expense and complexity of BSA circuitry, cluster-ICs are still widely used in modern circuit boards. Since combinational logic and 3-state cluster nets exist within cluster interconnect, in order to test all detectable faults in inter-IC nets that include cluster-ICs, newly identified TPG requirements are used to guarantee fault coverage during the design of proposed BIST architecture. This architecture contains a two-level C-TPG that generates constrained pseudo-random patterns for boundary scan cells (BSCs) of cluster control cones, a D-TPG that generates patterns for BSCs of cluster data cones, and a look-up table which is programmed to select, for each BSC, a specific C-TPG or D-TPG stage whose content is shifted into that BSC. This test architecture provides a true BIST solution for cluster testing. The proposed methodology generates TPGs that (i) guarantee the avoidance of multi-driver conflicts when testing via BSA, (ii) guarantee the detection of all testable interconnect faults, (iii) have low area overheads, and (iv) have short test lengths.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 23
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 3 (1992), S. 33-43 
    ISSN: 1573-0727
    Keywords: Aliasing probability ; built-in self-test ; compaction by counter ; edge counting ; linear feedback shift register ; one's counting ; signature analysis ; test response compaction ; transition counting
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract According to some recently published results, counter-based compaction outperforms compaction by linear feedback shift registers. These results, however, are based on oversimplified assumptions. In this paper, we discuss an error model to describe the behavior of a faulty circuit under test. We study the three most popular counter-based compaction schemes, (i.e., one's counting, transition counting and edge counting). Using Markov processes we derive equations for iterative computations of exact aliasing probability for any test session length and determine the asymptotic probability of aliasing. For one's counting, we also present a closed form expression that, for any test session length, gives the exact aliasing probability. Finally, we present some examples to compare the aliasing in the counter-based compaction and compaction by a linear feedback shift register. These examples indicate that aliasing by LFSRs is more “predictable” than aliasing by counters.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 24
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 4 (1993), S. 71-89 
    ISSN: 1573-0727
    Keywords: BILBO design system ; built-in self-test ; synthesis for testability ; test scheduling
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract There are usually many different ways to make a digital circuit testable using the BILBO methodology. Each solution can have different values of test time and area overhead. A design system based on the BILBO methodology has been developed that can efficiently explore the testable design space to generate a family of designs ranging from the minimal test time design to the minimal area overhead design. A designer can select an appropriate design based on trade-offs between test time and area overhead. The branch and bound technique is employed during the exploring process to prune the design space. This significantly reduces the execution time of this process. To effectively bound the exploring process, a very efficient test scheduler has been developed. Unlike previous approaches, this new test scheduler can process a partially testable design as well as a complete testable design. A test schedule for a design is constructed incrementally. The test scheduling procedures are presented along with experimental results that show that this test scheduler usually outperforms existing schedulers. In many cases, it generates an optimal test schedule. Experiments have been performed on several circuits generated by MABAL, a CAD synthesis tool, to demonstrate the performance and practicality of this system.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 25
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 4 (1993), S. 151-158 
    ISSN: 1573-0727
    Keywords: Aliasing probability ; built-in self-test ; multiple input signature analysis ; test data compaction
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract In built-in self-test for logic circuits, test data reduction can be achieved using a linear feedback shift register. The probability of this data reduction allowing a faulty circuit to be declared good is the probability of aliasing. This article examines aliasing in circular multiple-input shift-registers (MISRs), under the independent bit error model. We present an exact closed form expression for aliasing probability without assuming equiprobable bit error probabilities. We show that the aliasing probability can be much larger than its asymptotic value. Irrespective of the register length we prove that for a circular MISR, when two inputs are used for testing out ofm possible inputs, high minimum spatial separations between inputs result in low aliasing probabilities. We also show that for equiprobable errors an m-bit circular MISR can be replaced with a set ofm single-bit MISRs without affecting aliasing probability or adding any additional logic, to reduce the propagation delay due to feedback path. The above features can be used as criteria for the MISR design.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 26
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 4 (1993), S. 159-180 
    ISSN: 1573-0727
    Keywords: Board and system test ; boundary scan ; built-in self-test ; design-for-test ; test controllers ; test program synthesis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract BOLD is a system that supports several test aspects of digital hardware units, such as chips, modules (boards), and systems. BOLD consists of three main components, namely a design methodology, special hardware structures, and special test languages and their associated compilers. The goal of the BOLD system is to make it feasible for an engineer to efficiently develop high quality tests for hardware units. These tests usually consist of (1) tests for faults that are internal to a unit and that are supported by one or more design-for-test or built-in self-test methodologies, and (2) interconnect tests between units. The main idea behind BOLD is to be able to easily compose tests for low level hardware units to create a test for a higher level unit. The BOLD system employs a hierarchical design-for-test system design methodology. Each hardware unit is made testable by incorporating a test controller within its design. The controllers communicate among themselves via test busses, including, e.g., the IEEE 1149.1 boundary scan test bus. The BOLD methodology is supported by a family of high level languages used to describe the testability aspects of chips and modules. These test descriptions are automatically synthesized into test programs. Executing a test program on a test controller at one level of the hierarchy controls the testing of hardware at lower levels of the hierarchy. The compiled test consists of test instructions and test data, gleaned automatically from the high level test program descriptions. This article describes the test hardware configuration used, the test languages, the organization of the test descriptions, and how these descriptions are synthesized (translated) into executable test programs. The focus of this article is on the automated test program synthesis techniques employed in BOLD that can greatly reduce test program development costs.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
  • 27
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 5 (1994), S. 83-90 
    ISSN: 1573-0727
    Keywords: Aliasing probability ; built-in self-test ; linear feedback shift register ; scan path ; signature analysis ; test response compaction
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract In this article we address the problem of compacting test response data captured in scan paths. We consider linear compactors, e.g., multiple-input signature registers, and the effect of their characteristic polynomials on the number of aliased faults. The novelty of our analysis lies in that it is based on a realistic error model which takes into account the time correlation among the errors in the test response data fed to the compactor. Such a correlation does exist in scan-based compaction, but has not been considered previously. Based on our analysis, we derive three conditions that should be satisfied to minimize aliasing. They impose little restriction on circuit design.
    Type of Medium: Electronic Resource
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
Close ⊗
This website uses cookies and the analysis tool Matomo. More information can be found here...