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  • Articles  (9)
  • Built-in self-test  (9)
  • Springer  (9)
  • 1990-1994  (9)
  • 1985-1989
  • 1960-1964
  • 1950-1954
  • Electrical Engineering, Measurement and Control Technology  (9)
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  • Articles  (9)
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Keywords
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  • Springer  (9)
Years
  • 1990-1994  (9)
  • 1985-1989
  • 1960-1964
  • 1950-1954
  • 1995-1999  (2)
Year
Topic
  • Electrical Engineering, Measurement and Control Technology  (9)
  • 1
    Electronic Resource
    Electronic Resource
    A class of two-dimensional cellular automata and their applications in random pattern testing (1994)
    Springer
    Journal of electronic testing 5 (1994), S. 67-82 
    Details
    ISSN: 1573-0727
    Keywords: Built-in self-test ; cellular automata (CA) ; pseudo-random patterns ; 2-D CA
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A basic framework to characterize the behavior of two-dimensional (2-D) cellular automata (CA) has been proposed. The performance of the regular structure of the 2-D CA has been evaluated for pseudo-random pattern generation. The potential increase in the local neighborhood structure for 2-D CA has led to better randomness of the generated patterns as compared to LFSR and 1-D CA. The quality of the random patterns generated with 2-D CA based built-in-self-test (BIST) structure has been evaluated by comparing the fault coverage on several benchmark circuits. Also a method of synthesizing 2-D CAs to generate patterns of specified length has been reported. The patterns generated can serve as a very good source of random two-dimensional sequences and also variable length parallel pattern generation having virtually nil correlation among the bit patterns.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00971964
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  • 2
    Electronic Resource
    Electronic Resource
    Parity bit calculation and test signal compaction for BIST applications (1992)
    Springer
    Journal of electronic testing 3 (1992), S. 45-52 
    Details
    ISSN: 1573-0727
    Keywords: Built-in self-test ; parity bit ; pseudo-exhaustive tests ; test response compression
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Parity bit checking and pseudo-exhaustive testing are two design techniques which have been widely discussed in the BIST literature but have seldom been employed in practice because of the exponential nature of the processes involved. In this paper we describe several procedures designed to avoid these exponential explosions. Specifically we show how the parity of a large combinational function can (often) be quickly calculated. This is accomplished by an examination of the circuit realization itself particularly with regard to the connectivity between the various inputs and outputs. We then show how this same approach can be used to partition circuits so that they can be tested efficiently with a relatively small number of test patterns. Using these methods we were able to calculate the parity bits for more than 80% of ISCAS benchmark circuits' outputs. Interestingly enough, only 15% of these outputs were found to be parity-odd, but for these cases high fault coverage was invariably found to result. Several examples are included.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00159830
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  • 3
    Electronic Resource
    Electronic Resource
    BIDES: A BIST design expert system (1991)
    Springer
    Journal of electronic testing 2 (1991), S. 165-179 
    Details
    ISSN: 1573-0727
    Keywords: Built-in self-test ; design for testability ; knowledge-based expert system ; pseudorandom testing
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract BIDES is an expert system for incorporating BIST into a hardware design that is described in VHDL. Based on the BILBO technique, the BIDES system allocates pseudorandom pattern generators and signature analysis registers to each combinational logic module in a design in such a way that given constraints on testing time and hardware overhead are satisfied. This assignment is performed using the iterative process of regeneration and evaluation of various BIST implementations. In order to effectively perform regeneration, an abstraction hierarchy for a BIST design is introduced and a hierarchical planning technique is employed using this structure. This formulation also leads to an easily modifiable system. Prolog is used for implementing the system.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00133501
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  • 4
    Electronic Resource
    Electronic Resource
    Cyclic code weight spectra and BIST aliasing (1991)
    Springer
    Journal of electronic testing 2 (1991), S. 153-163 
    Details
    ISSN: 1573-0727
    Keywords: Built-in self-test ; compaction aliasing probability ; linear code spectra ; multiple input signature analysis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract In built-in self-test for logic circuits, test data reduction can be achieved using a linear feedback shift register. The probability that this data reduction will allow a faulty circuit to be declared good is the probability of aliasing. Based on the independent bit-error model, we show that the code spectra for the cyclic code generated by the feedback polynomial can be used to obtain an exact expression for the aliasing probability of a multiple input signature register when the test length is a multiple of the cycle length. Several cases are examined and, as expected, primitive feedback polynomials provide the best performance. Some suggestions to avoid peaks in the aliasing probability are given.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00133500
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  • 5
    Electronic Resource
    Electronic Resource
    Constrained parity testing (1991)
    Springer
    Journal of electronic testing 2 (1991), S. 279-291 
    Details
    ISSN: 1573-0727
    Keywords: Built-in self-test ; compaction testing ; parity testing ; signature analysis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A generalized testing technique called constrained parity testing is presented for detecting multiple stuck-at faults in any single-output irredundant combinational network by verifying the subparities of the network. Implementation independent testability conditions are established for single- and multiple-input stuck-at faults. A spanning parity signature (SPS) is introduced to detect vacuous faults, which include all the input stuck-at faults and a majority of all other multiple stuck-at faults. The SPS is considered for testing all stuck-at faults in networks with small numbers of fanout lines, and a method of deriving tests for nonvacuous faults is proposed. For networks with large fanouts, a hybrid scheme by combining with syndrome testing is suggested to eliminate or reduce the need for expensive fault simulation. The proposed technique is a theoretical generalization of many existing methods and offers advantages such as versatility, flexibility, low test volume, low test time, high fault coverage, and reduced fault simulation and test generation costs.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00135443
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  • 6
    Electronic Resource
    Electronic Resource
    Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling (1991)
    Springer
    Journal of electronic testing 2 (1991), S. 351-372 
    Details
    ISSN: 1573-0727
    Keywords: Built-in self-test ; design-for-testability ; iterative logic array ; pseudo-exhaustive test ; test generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract In this article we discuss a test generation, design-for-testability and built-in self-test methodology for two-dimensional iterative logic arrays (ILAs) that perform arithmetic functions. Our approach is unique because a single graph labeling procedure is used to generate test vectors, implement design-for-testability as well as design the circuitry for built-in self-test. The graph labeling is based on mathematical properties of full-addition such as symmetry and self-duality. Circuit modifications are introduced by a systematic procedure based on the graph labeling, that enable them to be tested with a fixed number of tests irrespective of their size. The approach is novel as it also greatly simplifies the processes of on-chip test vector generation and response comparison that are necessary for built-in self-test. Each circuit module is tested in a pseudo-exhaustive manner with deterministic as opposed to random test sequences. This results in a comprehensive test of the circuit for which built-in self-test is designed.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00135230
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  • 7
    Electronic Resource
    Electronic Resource
    Optimizing error masking in BIST by output data modification (1990)
    Springer
    Journal of electronic testing 1 (1990), S. 59-71 
    Details
    ISSN: 1573-0727
    Keywords: Built-in self-test ; error masking ; improving fault coverage ; output data compaction
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract The error masking in conventional built-in self-test schemes is known to be around 2−m when the output data is compacted in an m-bit multi-input linear feedback shift register. In the recent years, several schemes have been proposed which claim to reduce the error masking in a significant way while maintaining the need for a small overhead. In this paper, a completely new scheme for reducing error masking is proposed. Unlike the previous schemes in the literature, the new scheme is circuit-dependent and uses the concept of output data modification. This concept suggests modifying the original test output sequence before compaction, in order to obtain a new sequence with a reduced error masking probability. It is shown that the output data modification scheme provides a simple trade-off between the desired error masking which could run into (21thousands) and the area overhead needed (which would usually be equal to a 16 or 32 bit multi-input linear feedback shift register) for this masking. Finally, a formal proof is presented which establishes that despite circuit-dependency, the proposed scheme will on the average always lead to the desired error masking.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00134015
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  • 8
    Electronic Resource
    Electronic Resource
    Exact probabilistic testability measures for multi-output circuits (1990)
    Springer
    Journal of electronic testing 1 (1990), S. 229-234 
    Details
    ISSN: 1573-0727
    Keywords: Built-in self-test ; CAD tools ; probabilistic testability analysis ; test-pattern generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract The computation of probabilistic testability measures has become increasingly important and some methods have been proposed, although the exact solution of the problem is NP-hard. An exact analytical method for singleoutput combinational circuits is extended to deal with multi-output circuits. Such circuits are reduced to singleoutput ones by introducing a dummy gate, the “X-gate,” and applying to the resulting graph the analysis based on supergates.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00153860
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  • 9
    Electronic Resource
    Electronic Resource
    Exact probabilistic testability measures for multi-output circuits (1990)
    Springer
    Journal of electronic testing 1 (1990), S. 229-234 
    Details
    ISSN: 1573-0727
    Keywords: Built-in self-test ; CAD tools ; probabilistic testability analysis ; test-pattern generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract The computation of probabilistic testability measures has become increasingly important and some methods have been proposed, although the exact solution of the problem is NP-hard. An exact analytical method for singleoutput combinational circuits is extended to deal with multi-output circuits. Such circuits are reduced to singleoutput ones by introducing a dummy gate, the “X-gate,” and applying to the resulting graph the analysis based on supergates.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00938686
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