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  • 1
    Electronic Resource
    Electronic Resource
    Springer
    Mathematische Annalen 195 (1971), S. 143-148 
    ISSN: 1432-1807
    Source: Springer Online Journal Archives 1860-2000
    Topics: Mathematics
    Type of Medium: Electronic Resource
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  • 2
    Electronic Resource
    Electronic Resource
    Springer
    Aequationes mathematicae 25 (1982), S. 274-288 
    ISSN: 1420-8903
    Keywords: Primary 08A25, 02C05
    Source: Springer Online Journal Archives 1860-2000
    Topics: Mathematics
    Notes: Abstract LetA be a finite set,n≥1 andD⊆A n. We say thatf :D →A is a functionally complete partial operation of size |D| if eachf*:A n →A agreeing withf onD is functionally complete. Such an operation of sized represents thus a family of $$|A|^{(|A|^n - d)} $$ functionally complete operations. We investigate the least possible size of functionally complete partial groupoids. Such groupoids not defined on a row or column have size either |A|+1 or |A|+2 or are of size at least 2|A|−2. We prove that |A|+1 is the least size of such a groupoid and completely determine those of size |A|+1. As one might expect, these groupoids are very special. This study shows how surprisingly little information is needed to ensure that a groupoid is functionally complete and, at the same time, gives a description of large classes of functionally complete groupoids.
    Type of Medium: Electronic Resource
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  • 3
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 2 (1991), S. 279-291 
    ISSN: 1573-0727
    Keywords: Built-in self-test ; compaction testing ; parity testing ; signature analysis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A generalized testing technique called constrained parity testing is presented for detecting multiple stuck-at faults in any single-output irredundant combinational network by verifying the subparities of the network. Implementation independent testability conditions are established for single- and multiple-input stuck-at faults. A spanning parity signature (SPS) is introduced to detect vacuous faults, which include all the input stuck-at faults and a majority of all other multiple stuck-at faults. The SPS is considered for testing all stuck-at faults in networks with small numbers of fanout lines, and a method of deriving tests for nonvacuous faults is proposed. For networks with large fanouts, a hybrid scheme by combining with syndrome testing is suggested to eliminate or reduce the need for expensive fault simulation. The proposed technique is a theoretical generalization of many existing methods and offers advantages such as versatility, flexibility, low test volume, low test time, high fault coverage, and reduced fault simulation and test generation costs.
    Type of Medium: Electronic Resource
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  • 4
    Electronic Resource
    Electronic Resource
    Springer
    International journal of parallel programming 6 (1977), S. 151-163 
    ISSN: 1573-7640
    Keywords: Switching theory ; logic design ; combinational circuits ; Boolean algebra ; circuit simplication
    Source: Springer Online Journal Archives 1860-2000
    Topics: Computer Science
    Notes: Abstract A new notation for a NAND operator is proposed, based on the prefix Polish notation following the style of Lukasiewicz. There is a direct one-to-one correspondence between the operators in the resulting system and gates in a circuit realization if identical subfunctions are recognized. An axiom set for the Boolean algebra based on this operator is given, and the axiomatic derivation of the algebra is demonstrated. A number of results concerning circuit manipulation, redundant sets of gate inputs, and necessary and sufficient conditions for the relocation of certain gate inputs are presented, and their use demonstrated by a number of examples.
    Type of Medium: Electronic Resource
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  • 5
    Publication Date: 2011-02-22
    Description: This paper presents some new considerations for spectral techniques for classification of Boolean functions. These considerations incorporate discussions of the feasibility of extending this classification technique beyond n=5. A new implementation is presented along with a basic analysis of the complexity of the problem. We also note a correction to results in this area that were reported in previous work.
    Print ISSN: 1065-514X
    Electronic ISSN: 1563-5171
    Topics: Electrical Engineering, Measurement and Control Technology
    Published by Hindawi
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