ALBERT

All Library Books, journals and Electronic Records Telegrafenberg

X
feed icon rss

Your email was sent successfully. Check your inbox.

An error occurred while sending the email. Please try again.

Proceed reservation?

Export
Filter
  • Articles  (15)
  • built-in self-test  (15)
  • 1995-1999  (15)
  • 1945-1949
  • Electrical Engineering, Measurement and Control Technology  (15)
Collection
  • Articles  (15)
Source
Keywords
Publisher
Years
Year
Topic
  • Electrical Engineering, Measurement and Control Technology  (15)
  • 1
    Electronic Resource
    Electronic Resource
    A new reconfigurable Test Vector Generator for built-in self-test applications (1996)
    Springer
    Journal of electronic testing 8 (1996), S. 153-164 
    Details
    ISSN: 1573-0727
    Keywords: cellular automata ; test vector generator ; built-in self-test ; rank order clustering
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper proposes a new approach to designing a BIST Test Vector Generator (TVG) for random vector-resistant circuits based on reconfigurable Cellular Automata Registers (CARs). Each CAR configuration is constructed by combining rules 90 and 150 and the same approach can also be applied to the Linear Feedback Shift Register (LFSR). The TVG thus designed is able to produce 100% fault coverage with short test time at the cost of low area overhead. To achieve this objective, a new method called the Rank Order Clustering (ROC) method, is introduced in order to fix a number of inputs at certain values when generating pseudorandom vectors. It is shown that the ROC method is very simple and efficient in fixing inputs at these values in terms of complexity. Experimental results have been conducted to demonstrate the applicability of the proposed approach in terms of hardware size and test application time.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF02341821
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 2
    Electronic Resource
    Electronic Resource
    Integration of partial scan and built-in self-test (1995)
    Springer
    Journal of electronic testing 7 (1995), S. 125-137 
    Details
    ISSN: 1573-0727
    Keywords: built-in self-test ; design for testability ; partial scan ; test points
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Partial-Scan based Built-In Self-Test (PSBIST) is a versatile Design for Testability (DFT) scheme, which employs pseudo-random BIST at all levels of test to achieve fault coverages greater than 98% on average, and supports deterministic partial scan at the IC level to achieve nearly 100% fault coverage. PSBIST builds its BIST capability on top a partial scan structure by adding a test pattern generator, an output data compactor, and a PSBIST controller in a way similar to that of deriving a full scan BIST from a full scan structure. However, to make the scheme effective, there is a minimum requirement regarding which flip-flops in the circuit should be replaced by scan flip-flops and/or initialization flip-flops. In addition, test arents are usually added to boost the fault coverage to the range of 95 to 100 percent. These test points are selected based on a novel probabilistic testability measure, which can be computed extremely fast for a special class of circuits. This ciass of circuits is precisely the type of circuits that we obtain after replacing some of the flip-flops.withscan and/or initilization flip-flops. The testability measure is also used for a very useful quick estimation of the fault coverage right after the selection of sean flip-flops, even before the circuit is modified to incorporate PSBIST capability. While PSBIST provides all the benefits of BIST, it incurs lower area overhead and performance degradation than full scan. The area overhead is further reduced when the boundary scan cells are reconfigured for BIST usage.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00993320
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 3
    Electronic Resource
    Electronic Resource
    Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults (1995)
    Springer
    Journal of electronic testing 7 (1995), S. 209-221 
    Details
    ISSN: 1573-0727
    Keywords: built-in self-test ; linear feedback shift register ; linear finite state machine ; linear hybrid cellular automata ; sequential fault ; transition capability
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper presents a combinatorial method of evaluating the effectiveness of linear hybrid cellular automata (LHCA) and linear feedback shift registers (LFSR) as generators for stimulating faults requiring a pair of vectors. We provide a theoretical analysis and empirical comparisons to see why the LHCA are better than the LFSRs as generators for sequential-type faults in a built-in self-test environment. Based on the concept of a partner set, the method derives the number of distinctk-cell substate vectors which have 22k , 1≤k≤[n/2], transition capability for ann-cell LHCA and ann-cell LFSR with maximum length cycles. Simulation studies of the ISCAS85 benchmark circuits provide evidence of the effectiveness of the theoretrical metric.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00995314
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 4
    Electronic Resource
    Electronic Resource
    Comments on “Aliasing Properties of Circular MISRs” (1995)
    Springer
    Journal of electronic testing 6 (1995), S. 139-140 
    Details
    ISSN: 1573-0727
    Keywords: Aliasing ; built-in self-test ; error models ; signature analysis ; test response compaction
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract The analysis of aliasing probability presented in a recent article, “Aliasing Properties of Circular MISRs” [1], is based on an error model that cannot adequately represent real circuits. We show why conclusions presented in [1] should not be used in practice, substantiating our claim with experimental results.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00993137
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 5
    Electronic Resource
    Electronic Resource
    GigaHertz MUX-DEMUX Chip with HF BIST (1997)
    Springer
    Analog integrated circuits and signal processing 12 (1997), S. 29-48 
    Details
    ISSN: 1573-1979
    Keywords: high frequency multiplexer/demultiplexer circuits ; built-in self-test
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Full functional test at speed, in-situ is an ideal choice for use for detection of errors in circuit behaviour for high speed broadband communication circuits and to avoid test set-up disturbances on high frequency signals. This article presents a novel technique to solve the high frequency test of Gbit/s data rate Time-Division Multiplexer/Demultiplexer circuits. This in-situ test technique is based on conventional pseudo-random sequence generation and signature analysis. By linear feedback interconnect and reusable architecture the multiplexer/demultiplexer circuits can operate as generator/analyser with minimal degeneration of bit shift rate. Circuit simulation showed that the system operates correctly with a clock frequency up to 3 GHz in a silicon bipolar technology with a current gain cut-off frequency f T = 15 GHz.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1013226817487
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 6
    Electronic Resource
    Electronic Resource
    Scalable Test Generators for High-Speed Datapath Circuits (1998)
    Springer
    Journal of electronic testing 12 (1998), S. 111-125 
    Details
    ISSN: 1573-0727
    Keywords: built-in self-test ; carry lookahead ; datapath circuits ; on-line testing ; scalability ; test generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper explores the design of efficient test sets and test-pattern generators for on-line BIST. The target applications are high-performance, scalable datapath circuits for which fast and complete fault coverage is required. Because of the presence of carry-lookahead, most existing BIST methods are unsuitable for these applications. High-level models are used to identify potential test sets for a small version of the circuit to be tested. Then a regular test set is extracted and a test generator TG is designed to meet the following goals: scalability, small test set size, full fault coverage, and very low hardware overhead. TG takes the form of a twisted ring counter with a small decoder array. We apply our technique to various datapath circuits including a carry-lookahead adder, an arithmetic-logic unit, and a multiplier-adder.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008242108853
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 7
    Electronic Resource
    Electronic Resource
    A Bist Scheme for Non-Volatile Memories (1998)
    Springer
    Journal of electronic testing 12 (1998), S. 139-144 
    Details
    ISSN: 1573-0727
    Keywords: built-in self-test ; off-line testing ; non-volatile memories ; signature analysis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A new BIST scheme for on-chip testing of non-volatile memories and based on signature analysis is presented. The signature of the whole memory, whose content can be changed selectively by the user, is dynamically self-learned by the memory and it is saved in a dedicated memory location. Either such a signature can be externally compared with the expected one in order to check for the programming operation, or it can be used for comparison purposes when data retention must be self-tested.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008246209762
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 8
    Electronic Resource
    Electronic Resource
    Estimation of BIST Resources During High-Level Synthesis (1998)
    Springer
    Journal of electronic testing 13 (1998), S. 221-237 
    Details
    ISSN: 1573-0727
    Keywords: built-in self-test ; high-level synthesis ; estimation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Lower bound estimations of functional resources at various stages of high-level synthesis have been developed to guide synthesis algorithms toward optimal solutions. In this paper we present lower bounds on the number of test resources (i.e., registers that generate pseudo-random test patterns and/or compress test responses) required to test a synthesized data path using built-in self-test (BIST). The bounds on different types of test resources are proved to be individually achievable and experiments show that in most cases the bounds can be achieved simultaneously and with minimum number of functional registers. Efficient ways of computing the lower bounds are developed. The estimations are performed on scheduled data flow graphs with a given module assignment and provide a practical way of selecting or modifying module assignments and schedules such that the resulting synthesized data path requires a small number of BIST resources to test itself.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008329702151
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 9
    Electronic Resource
    Electronic Resource
    An Effective Multi-Chip BIST Scheme (1997)
    Springer
    Journal of electronic testing 10 (1997), S. 87-95 
    Details
    ISSN: 1573-0727
    Keywords: MCM testing ; built-in self-test ; DFT
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper addresses the general problem of module level test ofassembled Multi-Chip Modules (MCMs) and specifically the performancetest of such modules. It presents a novel solution based-on built-in self-test (BIST). This solutionaugments the conventional single-chip BIST approach, which is used to produce individual good dies, to an effective multi-chip BIST solution. The multi-chip BIST puts the entire module in a self-test mode. The self-test mode not only provides effective detection of static and dynamic faults, but also identifies the failed elements, i.e., bad dies or substrate. The multi-chip self-test scheme is based on pseudo-random test generation and uses multi-signature evaluation. The hardware design ofmulti-chip and single-chip self-test blocks is combined under one common architecture called the Dual BIST Architecture. The paper introduces the Dual BIST Architecture and demonstrates a set of design configurations to implement it. The presented BIST solution provides a reliable static and dynamic test at the module as well as the bare die levels.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008226715929
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 10
    Electronic Resource
    Electronic Resource
    Multichip Module Diagnosis by Product-Code Signatures (1997)
    Springer
    Journal of electronic testing 10 (1997), S. 127-136 
    Details
    ISSN: 1573-0727
    Keywords: Multichip Module test and diagnosis ; system diagnosis ; built-in self-test ; signature analysis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A system diagnosis technique for multichip module (MCM) ispresented. The proposed technique uses built-in probes for monitoringinternal responses and, with a signature analysis scheme based onerror correcting codes, identifies the probes where erroneous test responses have been detected. Conceptsfrom system diagnosis is used in conjunction withsignature analysis in developing the proposed MCM diagnosistechnique, where the resulting patterns of the faulty probes are usedin the identification of the faulty submodules (dies). The proposedtechnique offers a diagnostic capability in system functional test.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008234917747
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 11
    Electronic Resource
    Electronic Resource
    Exhaustive and Near-Exhaustive Memory Testing Techniques and their BIST Implementations (1997)
    Springer
    Journal of electronic testing 10 (1997), S. 215-229 
    Details
    ISSN: 1573-0727
    Keywords: memory testing ; pattern sensitive faults ; built-in self-test ; exhaustive codes ; near-exhaustive codes
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract In this work we investigate the problem of detection and location ofsingle and unlinked multiple k-coupling faults in n × 1 random-access memories (RAMs). This fault model covers allcrosstalks between any k cells in n × 1 RAMs. The problem of memory testing has been reduced to the problem of the generationof (n,k-1)-exhaustive backgrounds. We have obtained practical test lengths, for a memory size around 1 M, for detecting up to6-couplings by exhaustive tests and up to 9-couplings bynear-exhaustive tests. The best known test algorithms up to nowprovide for the detection of 5-couplings only in a 1 M memory, usingexhaustive tests. Beyond these parameters, test lengths wereimpractical. Furthermore, our method for generation of(n,k-1)-exhaustive backgrounds yields short test lengths givingrise to considerably shorter testing times than the present mostefficient tests for large n and for k greater than 3. Our test lengths are 50% shorter than other methods for the case of detectingup to 5-couplings in a 1 Mbit RAM. The systematic nature of both ourtests enables us to use a built-in self-test (BIST) scheme, for RAMs, with low hardware overhead. For a 1Mbit memory, the BIST areaoverhead for the detection of 5-couplings is less than 1% for SRAMand 6.8% for a DRAM. For the detection of 9-couplings with 99% or higher probability, the BIST area overhead is less than 0.2% forSRAM and 1.5% for DRAM.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008215624768
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 12
    Electronic Resource
    Electronic Resource
    BIST Pattern Generators Using Addition and Subtraction Operations (1997)
    Springer
    Journal of electronic testing 11 (1997), S. 69-80 
    Details
    ISSN: 1573-0727
    Keywords: accumulator ; adder ; built-in self-test ; pattern generator ; subtracter
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Configurations of adders, subtracters, or arithmetic logic units andregisters, which are available in many data paths, can be utilized togenerate patterns and to compact test responses. This paper analyzesthe pattern sequences generated by configurations with differenttypes of adders and subtracters. For many different seeds andconstant input values, these pattern generators can produce asequence of all possible patterns. Moreover, k-bit patterngenerators that take into account the overflow or underflow bit cangenerate bit sequences that all have period 2 k -1. Thus, theperiodicity of these pattern generators is the same as that of a k-bit linear feedback shift register with a primitivecharacteristic polynomial. Experimental results show that theproduced pattern sequences achieve similar fault coverage aspseudorandom sequences and require about the same testlength. Compared to the well-known self-test methods that insert testregisters, the approach using available arithmetic units saves theadditional gates that are needed to implement test registers, and itavoids performance degradation due to additional delays.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008299817888
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 13
    Electronic Resource
    Electronic Resource
    Transparent random access memory testing for pattern sensitive faults (1996)
    Springer
    Journal of electronic testing 9 (1996), S. 251-266 
    Details
    ISSN: 1573-0727
    Keywords: random access memory ; memory testing ; transparent memory testing ; built-in self-test ; pseudoexhaustive memory testing ; pattern sensitive faults ; signature analysis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper presents a new methodology for RAM testing based on the PS(n, k) fault model (the k out of n pattern sensitive fault model). According to this model the contents of any memory cell which belongs to an n-bit memory block, or the ability to change the contents, is influenced by the contents of any k -1 cells from this block. The proposed methodology is a transparent BIST technique, which can be efficiently combined with on-line error detection. This approach preserves the initial contents of the memory after the test and provides for a high fault coverage for traditional fault and error models, as well as for pattern sensitive faults. This paper includes the investigation of testing approaches based on transparent pseudoexhaustive testing and its approximations by deterministic and pseudorandom circular tests. The proposed methodology can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00134690
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 14
    Electronic Resource
    Electronic Resource
    An Implementation Approach of the IEEE 1149.1 for the Routing Test of a VLSI Massively Parallel Architecture (1998)
    Springer
    Journal of electronic testing 12 (1998), S. 171-185 
    Details
    ISSN: 1573-0727
    Keywords: MIMD architectures ; routing test ; IEEE 1149.1 ; built-in self-test ; diagnosis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper presents an implementation approach for the test of routers in a fine grain massively parallel architecture. First, an ad hoc test technique which diffuses test messages router by router is analyzed. Even though the technique does not add hardware, it is shown inefficient and not applicable due to practical constraints such as the limited number of pins of the chip implementing the machine. Based on a hierarchical implementation of the IEEE 1149.1 standard, two approaches are proposed and compared in terms of the area overhead, the overall test time and the flexibility in applying tests and diagnosing the routers inside the machine. The basic idea for both approaches is to construct groups of basic cells which are driven by the same test block and compare their test results after the same test vectors are applied at each cell input. The two approaches differ in the granularity of a basic cell. The choice of an implementation approach is not trivial. It is shown that each approach presents better performance than the other, that is, the approach which allows better fault coverage and less test time requires more silicon and less diagnostic possibilities compared to the second approach.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008216431810
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 15
    Electronic Resource
    Electronic Resource
    An IEEE 1149.1 Compliant Test Control Architecture (1998)
    Springer
    Journal of electronic testing 13 (1998), S. 273-297 
    Details
    ISSN: 1573-0727
    Keywords: test control ; boundary scan ; built-in self-test ; design-for-test ; test bus ; local test control ; distributed test control ; dynamic test control
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper deals with a design methodology and associated architecture to support the control of on-chip DFT and BIST hardware. The work is general in that it supports numerous test methods, such as partial and full scan, multiple and reconfigurable scan chains, and both test per clock BIST and scan BIST. The results presented here are compatible with the IEEE 1149.1 boundary scan architecture. The work is based on a hierarchical control methodology that includes systems, PCBs and MCMs. Various options for assigning control functions to be on-chip or off-chip are described. A new, partially distributed test control architecture is introduced that includes an internal test bus and distributed local controllers. There are three main modes of control of test resources, namely local static control, dynamic control and global static control. We show how the control mechanism can be implemented together with the IEEE 1149.1 test protocol. The synthesis of the on-chip test control hardware has been automated in a system called CONSYST.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008385819898
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
Close ⊗
This website uses cookies and the analysis tool Matomo. More information can be found here...