ALBERT

Description: A common-mode (CM) active filter was designed in a compact package to suppress CM conducted emissions at a switching mode power supply (SMPS). Based on the analytical expressions considering both stability and performance, the design and optimization rules for the proposed active filter have been presented. After verifying its performance by measurements using vector network analysis, the proposed filter was installed in a 200-W SMPS board with 64 and 110 kHz switching frequencies, demonstrating its usefulness by experiments. The performance degradation due to the magnetic saturation and the AEF grounding impedance was also analyzed and investigated.

Description: A kind of low-cost electric and magnetic field simulators, which are used to produce simulative lightning electromagnetic pulse (LEMP) with adjustable waveforms and intensity output, are presented. The lightning electric field can be produced within the GTEM cell by feed-in of impulse voltage output by a Marx generator. The lightning magnetic field can be produced within the coil by feed-in of surge current from the lightning surge generator. The simulated magnetic field is measured by a “B-dot” coil. The measured results show that the lightning electric field simulator and magnetic field simulator could provide relatively homogeneous LEMP environment within certain area in the GTEM cell and the coil within 3 dB deviation. The effects of the simulated lightning electric fields on some electronic devices and the influence of the turns and size of the coil on the homogeneity of the simulated magnetic fields are also investigated.

Description: This paper presents a detailed model of devices utilizing many nanotubes and the coupling between them based on the electromagnetic model of a device using one nanotube. Empirical equations are proposed to link the device conductance with the number of nanotubes per device. Then, a circuit model is developed to predict the effect of the number of nanotubes per device on the overall conductance, capacitance, and the frequency response of the device. A prototype structure is fabricated. Its performance is tested and compared with the proposed model, and it shows promising agreements. The model is flexible and can be integrated with quantum transport models.

Description: A full-wave analysis of the fundamental quasi-TEM modes supported by multiple graphene nanoribbons above a ground plane is presented, aimed at characterizing crosstalk in graphene multiconductor lines. A method-of-moments discretization of the relevant electric-field integral equation is performed. Assuming first a local scalar conductivity, an efficient spatial-domain approach with subsectional basis functions is assuming first a local scalar conductivity, a spatial-domain approach with subsectional basis functions is developed. This allows for the efficient treatment of nanoribbons with wide transverse separations, and can be expanded to include in the simulation model spatial nonuniformity of the graphene conductivity. This spatial-domain formulation is then extended to treat the case of weakly nonlocal conductivity, via an original integro-differential approach derived by approximating a recent full spectral graphene conductivity model in the limit of low wavenumbers. Numerical results are provided for propagation constants and characteristic impedances of two identical coupled graphene nanoribbons; on this basis, a crosstalk analysis is performed by means of the modal decomposition method.

Description: Crosstalk within cable bundles can degrade system performance. In aircraft systems that use shielded twisted pairs, the crosstalk occurs primarily in the connector where individual signal wires are not shielded or twisted. In many cases, the parameters which determine crosstalk within the connector are unknown because the connector is closed and wires cannot be easily accessed. Expanding on prior research [14] , a methodology for measuring coupling parameters and modeling crosstalk within aircraft cable connectors at low frequencies (〈400 MHz) was developed. The values of mutual inductance and capacitance were extracted from measurements made with a vector network analyzer (VNA). The characteristics of the individual wires were extracted from VNA-measured TDR response. The accuracy of the model was evaluated through comparison of simulated and measured results. Additionally, a closed-form solution was developed to estimate the worst-case envelope of the differential crosstalk. The calculated results match the measured peak values well. This worst-case crosstalk estimate allows effective evaluation of the impact of crosstalk within different connectors. The developed method can be effective for analyzing complex aircraft cable assemblies and connectors without requiring extensive knowledge of the assembly procedure.

Description: Surface roughness topography of printed circuit boards (PCBs) needs to be included in signal integrity simulations in order to accurately predict the insertion loss of the structure and its delay time. An effective roughness dielectric (ERD) model can be used to substitute an inhomogeneous interface between copper foil and laminate dielectric in a PCB. Herein, this approach is tested for verification using 3-D full-wave numerical simulations. These ERD layers with the appropriate complex permittivity are included in the modeling of stripline examples. The parameters of an ambient laminate dielectric refined from conductor roughness in the stripline are determined using differential extrapolation roughness measurement technique. The agreement of the results of 3-D full-wave modeling simulations and measurements on multiple test structures justifies the proposed approach. Based on the extracted ERD parameters “design curves” can be built and used in numerical simulations of PCB high-speed designs.

Description: A small amount of jitter can quickly eat up timing budgets and create timing issues. Precise characterization of deterministic and crosstalk-induced jitter can help isolate and solve issues within high-speed links. Characterizing deterministic and crosstalk-induced jitter is challenging, however, because many types of jitter work together to create the overall jitter profile. Methods are presented in this paper to characterize the deterministic and crosstalk-induced jitter from measurements of total jitter. An improved tail-fit deconvolution method is proposed for characterizing the impact of deterministic jitter in the presence of random jitter. The contribution of random jitter to total jitter is found first, and then that contribution is accounted for to find deterministic jitter. A Wiener filter deconvolution method is also presented for extracting the characteristics of crosstalk-induced jitter from measurements of total jitter made when the crosstalk sources were and were not present. The Wiener filter allows for accurate deconvolution of the measured histograms for total jitter even in the presence of the measurement noise. The proposed techniques are shown to work well both in simulations and in measurements of a high-speed link.

Description: This paper explored the possibility of building channel emulators by utilizing fused deposition modeling (FDM) three-dimensional (3-D) printing technology. The FDM 3-D printing provides a rapid and economic method to produce parts with different shapes. An optimizing algorithm was developed for obtaining the printing pattern and loss profile. Parts with different dielectric constants and loss tangents can be printed. Those parts will be placed or directly printed on a low-loss transmission line to modify its transmission or reflection. As a result, different channel emulators can be built to emulate the S -parameter and eye diagrams of a target channel with the advantage of avoiding complicated electronic components and only being limited in the frequency range by the transmission line and attached connectors.

Description: In this paper, we present general considerations for the application of the multiconductor transmission-line theory for simulating shielded spacecraft harness cable assemblies. Some of the practical issues that occur in the modeling process of various components of cable assemblies in spacecraft applications, namely connectors, pigtails, and backshells are discussed. The overall transfer impedance of the assembly measured through a current injection with a pseudomicrostrip line is used as a figure of merit to evaluate the total shielding provided by the harness. Some of the parameters of the model were available from the manufacturers’ datasheets, while others were determined either experimentally or empirically. The position of the cables along the cross section was randomly assigned by the simulation tool. In general, the obtained simulation results are found to be in reasonable agreement with the experimental data. It is found that the generally overlooked contact impedances between the cable shields and connectors play a significant role, especially at low frequencies. The presented simulation results also emphasize the importance of the inductance and resistance of the connector backshell interconnection to the spacecraft chassis.

Description: Encryptions are used in almost all standards to ensure the confidentiality of the data. Encryptions can be and indeed are implemented in the different layers of a network protocol stack. Conventional encryption performs the bitwise XOR operation between one message bit and one key stream bit to generate one ciphertext bit. Huo et al. have recently proposed to provide confidentialities on the user data by performing the phase encryption on the time domain OFDM samples in LTE system. Phase encryption is performed on the modulated symbols, different from the bit level of XOR encryption, i.e., stream cipher encryption. In this paper, we extend their study. We first generalize the phase encryption to general communication systems independent of the underlying modulation scheme. Then, we formulate the mathematical models for XOR and phase encryptions. Based on our model, we compare these two encryption methods in terms of their security and encryption efficiency. We also show phase encryption can resist traffic analysis attack when implemented in the physical layer. Finally, we conduct simulations to compare the performance of these two methods in terms of their decoding symbol error rate.

Description: In this paper, an adaptive hierarchical sparse grid collocation (ASGC) method combined with the discontinuous Galerkin time-domain method is leveraged to quantify the impacts of random parameters on the electromagnetics systems. The ASGC method approximates the stochastic observables of interest using interpolation functions over a set of collocation points determined by the Smolyak's algorithm integrated with an adaptive strategy. Instead of resorting to a full-tensor product sense, the Smolyak's algorithm constructs the collocation points in a hierarchical scheme with the interpolation level. Enhanced by an adaptive strategy, the Smolyak's algorithm will sample more points along important dimensions with sharp variations or discontinuities, resulting in a nonuniform sampling scheme. To flexibly handle different stochastic systems, either piecewise linear or Lagrange polynomial basis functions are applied. With these strategies, the number of collocation points is significantly reduced. The statistical knowledge of stochastic observables including the expected value, variance, probability density function, and cumulative distribution function are presented. The accuracy and robustness of the algorithm are demonstrated by various examples.

Description: Signal integrity (SI) analysis based on state-of-the-art measurements can be difficult to perform especially when the structures of interest are on inner layers of multilayer boards or are enclosed by IC packages. To enable an SI analysis in such cases the authors have recently developed a method that is based on the extraction of accurate simulation models from computed tomography (CT) scans. These models can be used in electromagnetic (EM) field simulators for computer-aided SI analyses. Such CT-based models include geometry variations or defects due to the manufacturing process so that computed EM field simulation results have a good correlation with common measurements. In order to identify the potential of the method an analysis of the required voxel resolution for the extraction of single-ended and differential striplines is presented. The analysis is based on the measurement uncertainty of length measurements in CT scans and an analysis of the propagation of uncertainty for the characteristic impedances of single-ended and differential striplines. This analysis shows that the voxel resolution of industrial CT scans is well suited for the extraction of accurate simulation models which can be used for an SI analysis.

Description: In the millimeter wave (mmW) frequency range, the root mean square height of the through silicon via (TSV) sidewall roughness is comparable to the skin depth, and hence, becomes a critical factor for TSV modeling and analysis. In this paper, the impact of the TSV sidewall roughness on electrical performance, such as the loss and impedance alteration in the mmW frequency range, is examined and analyzed. The second-order small analytical perturbation method is applied to obtain a simple closed-form expression for the power absorption enhancement factor of the TSV. In this study, we propose an electrical model of the TSV, which considers the TSV sidewall roughness effect, the skin effect, and the metal oxide semiconductor effect. The parameters of the proposed circuit model can be determined analytically; the accuracy of the model is validated through a comparison of circuit model behavior for full wave electromagnetic field simulations up to 100 GHz.

Description: Sample preparation plays an essential role in most biochemical reactions. Raw reactants are diluted to solutions with desirable concentration values in this process. Since the reactants, like infant’s blood, DNA evidence collected from crime scenes, or costly reagents, are extremely valuable, their usage should be minimized whenever possible. In this paper, we propose a two-phased reactant minimization algorithm (REMIA), for sample preparation on digital microfluidic biochips. In the former phase, REMIA builds a reactant-minimized interpolated dilution tree with specific leaf nodes for a target concentration. Two approaches are developed for tree construction; one is based on integer linear programming (ILP) and the other is heuristic. The ILP one guarantees to produce an optimal dilution tree with minimal reactant consumption, whereas the heuristic one ensures runtime efficiency. Then, REMIA constructs a forest consisting of exponential dilution trees to produce those aforementioned specific leaf nodes with minimal reactant consumption in the latter phase. Experimental results show that REMIA achieves a reduction of reactant usage by 32%–52% as compared with three existing state-of-the-art sample preparation approaches. Besides, REMIA can be easily extended to solve the sample preparation problem with multiple target concentrations, and the extended version also effectively lowers the reactant consumption further.

Description: The 3-D integrated dynamic random-access memory (DRAM) structure with a processor is being widely studied due to advantages, such as a large band-width and data communication power reduction. In these structures, the massive heat generation of the processor results in a high operating temperature and a high refresh rate of the DRAM. Thus, in the 3-D DRAM over processor architecture, temperature-aware refresh management is necessary. However, temperature determination is difficult, because in the 3-D DRAM, the temperature changes dynamically and temperature variation in a DRAM die is complicated. In this paper, a thermal guard-band set-up method for 3-D stacked DRAM is proposed. It considers the latency of the temperature data and the position difference between the temperature sensor and the DRAM cell. With this method, the data reliability of the on-chip temperature sensor-dependent adaptive refresh control is guaranteed. In addition, an efficient temperature sensor built-in and refresh control method is analyzed. The expected refresh power reduction is examined through a simulation.

Description: Design of power delivery system has great influence on the power management in many-core processor systems. Moving voltage regulators from off-chip to on-chip gains more and more interest in the power delivery system design, because it is able to provide fine-grained dynamic voltage scaling. Previous works are proposed to implement power efficient on-chip voltage regulators. It is important to analyze the characteristics of the entire power delivery system to explore the tradeoff between the promising properties and costs of employing on-chip voltage regulators, especially the on-chip buck converters. In this paper, we present a novel analysis and design optimization platform of power delivery system called power supply on-chip (PowerSoC). It employs an analytical model to provide an accurate and fast evaluation of important characteristics, e.g., power efficiency, output stability, and dynamic voltage scaling, for the entire power delivery system consisting of on-chip/off-chip buck converters and power delivery network. Based on our model, geometric programming is utilized to find the optimal design for different power delivery systems and explore the tradeoff of using on-chip converters. Compared with SPICE simulations, our model achieves a simulation time reduction of six to seven orders of magnitude within 5% model error for the characteristic evaluation of different power delivery systems. By using PowerSoC, various architectures of power delivery systems are optimized for power efficiency under constraints of output stability, area, etc. Simulation results show that the hybrid architecture, consisting of both on-chip and off-chip converters, achieves 1.0% power efficiency improvement and 66.4% area reduction of converters, compared to the conventional design. We conclude the hybrid architecture has potential for efficient dynamic voltage scaling, small area, and the adaptability of the change of power delivery network parasitic, but ca- eful account for the overhead of on-chip converters is needed.

Description: As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, fabricated ICs become more susceptible to wear-outs, causing operation failure. Even a single link failure within an on-chip fabric can halt communication between application blocks, which makes the entire chip useless. In this paper, we aim to make faulty chips designed with network-on-chip (NoC) communication usable. Specifically, we present fault-tolerant irregular topology-generation method for application-specific NoC designs. Designed NoC topology allows different routing path if there is a link failure on the default routing path. Additionally, we present a simulated annealing-based application mapping algorithm aiming to minimize total energy consumption of the NoC design. We compare fault-tolerant topologies with nonfault-tolerant application-specific irregular topologies on energy consumption, performance, and area using multimedia benchmarks and custom-generated graphs. Our results demonstrate that our method is able to determine fault-tolerant topologies with negligible area increase and better energy values.

Description: Three-dimensional (3-D) integration is an attractive technology platform for next-generation ICs. Despite the benefits offered by 3-D integration, test cost remains a major concern, and analysis and tools are needed to understand test flows and minimize test cost. We propose a generic cost model to account for various test costs involved in 3-D integration and present a formal representation of the solution space to minimize the overall cost. We present an algorithm based on A*—a best-first search technique—to obtain an optimal solution. An approximation algorithm with provable bounds on optimality is proposed to further reduce the search space. In contrast to prior work, which is based on explicit enumeration of test flows, we adopt a formal optimization approach, which allows us to select an effective test flow by systematically exploring an exponentially large number of candidate test flows. Experimental results highlight the effectiveness of the proposed method. Adopting a formal approach to solving the cost-minimization problem provides useful insights that cannot be derived via selective enumeration of a smaller number of candidate test flows.

Description: Power radiation and radiated coupling among different structures represent an important area for research study. The partial element equivalent circuit method (PEEC) is a powerful technique which bridges the gap between the electromagnetic and circuit theories. In this paper, we develop a new approach for PEEC to calculate the distributive power radiation and couplings. With this approach, formulations for both the radiated power and the transferred power can be evaluated. Further, the physical meanings of the power results are interpreted according to the conservation of energy law. We use electric dipoles, magnetic dipoles and patch antennas as well as coupled microstrip lines to benchmark the method. The approach can also be applied to EMC/EMI and other power dissipation computations.

Description: The coupling from electrostatic discharge (ESD) events is effectively calculated using the partial element equivalent circuit (PEEC) method, both in time and frequency domains. The PEEC method has several advantages in predicting dominant coupling sources and waveforms of ESD. Two victim structures were designed so that the inductive or capacitive coupling could be dominant. The calculation of ESD coupling is validated by comparison with measurements and the finite-element method solver in frequency domain. The waveform of the ESD inductive coupling is also validated with measurements and the finite-difference time domain solver in time domain.

Description: Time-domain channel characterization (TCC) for de-embedding of an asymmetric fixture is introduced. Two design criteria for the design of a 2x-thru are proposed. Error sensitivity regarding a small error in the S-parameters of the 1x-fixture is analyzed with an insertion loss error-coefficient and a return loss error-coefficient. The TCC procedure, including proposed design criteria and error sensitivity, is also introduced to reduce the error in the TCC application. Three different 2x-thru structures are investigated for the verification of the two proposed design criteria and analyzed for error sensitivity. Test fixtures on a printed circuit boards are fabricated for the experimental verification.

Description: A circuit model of multilayer electromagnetic bandgap (EBG) structure with application on bandgap aggregation design is investigated in this paper. A design concept for bandgap aggregation is merging the lowest two bandgaps into an equivalent wide bandgap by narrowing central passband. This goal could be achieved by optimizing pitch and arrangement of power/ground vias. The theoretical circuit model which only focuses on cutoff frequencies is proposed for efficient bandgap prediction. The accuracy of the proposed model is validated by comparison with full-wave simulation and measurement results. By using the circuit model, mechanism of bandgap aggregation can be explained well, and the influence of structural parameters can also be studied easily. Furthermore, effect on limiting excitation of propagation modes by narrowing central passband is also validated for merging adjacent bandgaps. Test boards with unit cell size 2.03 mm × 3.94 mm are fabricated and measured to validate the design concepts. Both simulation and measurement show the wide bandgap in insertion loss results, which ranges from 1.27 GHz to above 10 GHz by merging even higher bandgaps.

Description: The result of any measurement will only be of significance if the uncertainty of the measurement method can be specified concerning its influence quantities. In the case of CISPR compliant-radiated disturbance measurements, the result of the measurement is usually compared to a given limit line. For established test methods (ETM), this comparison can be done directly if the expanded measurement uncertainty falls below a value stated for a typical test facility by the standard. In this paper, the definitions and the classification the CISPR describes for ETM are applied to transverse electromagnetic (TEM) waveguide measurements. It is shown that the overall uncertainty of a typical TEM waveguide is slightly lower than that of a typical ETM.

Description: A new common-mode filter structure based on planar electromagnetic bandgap (EBG) technologies is designed, fabricated, and measured. It is based on a previously proposed geometry, implementing a sequence of two or more EBGs resonating at a filtering frequency; however, the new filter is placed on the top of the PCB as a standalone component, instead of being included within the PCB stack up. The filter can be easily removed and substituted by another one that is designed to filter a different frequency. The replacement design should maintain the same external size of the component as the original filter, which can be achieved by choosing the permittivity of the dielectric as well as the relationship among the EBG parameters appropriately. The electromagnetic behavior of the filter is simulated and a prototype structure is fabricated and measured. Results are compared to validate the design concept and procedure.

Description: Effects of transmit jitter on lossy clock channel are analyzed analytically by treating the 1010 input clock signal as a sinusoidal wave with a phase modulation that represents jitter. Jitter-to-amplitude-modulation transfer functions are derived for sinusoidal jitter, duty-cycle distortion (DCD), and random jitter (RJ) in terms of the signal transfer function or S-parameters. Input jitter is shown to induce amplitude modulation in the output signal as a result of channel dispersion, leading to voltage noise at the channel output. DCD- and RJ-induced voltage noises are found to scale uniquely with channel loss. To verify the theory, numerical simulations are performed on channels with different losses and at various data rates. The input clock signal is represented with a square wave, and the output signal is calculated by linear superposition of the channel step response. Theoretical and simulation results are found to be in excellent agreement.

Description: The jitter probability density function (PDF) at multistage output buffers due to supply voltage fluctuations is analytically derived. For experimental validation, an integrated circuit (IC) is designed, fabricated, and assembled in a printed circuit board (PCB). The on-chip supply voltage fluctuations are extracted from the simultaneous measurements at the pads on IC and PCB and used to calculate the jitter PDF of the multistage buffers. Also, characteristics of the output channels are measured and modeled with the separately designed channel pattern. Finally, the jitter PDFs for multistage buffers are calculated and compared with the measured jitter histograms.

Description: The analysis of electromagnetic coupling in nonlinear circuit simulations requires a bidirectional, fully consistent approach. Nonlinear responses of semiconductor devices in electronic circuit components can change the impedances seen at circuit nodes, changing the boundary conditions encountered by impressed electromagnetic fields and, thus, changing the characteristics of the energy coupled from these external fields into that circuit. It is important to include the coupling in the circuit simulation self-consistently because this allows us to accurately predict the responses to various EMI/EMC problems of interest. It is also important to predict circuit responses efficiently because that opens the door to statistical applications for the technique being used. In this paper, we review a technique that we have developed called A Thevenin Equivalent Network Approach. This approach is shown to be quite robust in that it is computationally efficient; it can be implemented in a variety of commonly available circuit solving codes; it already includes a few additional techniques required to enhance its implementation in those codes; and it is quite accurate.

Description: This paper presents a novel approach to minimize the radio frequency (RF)-induced heating from external fixation devices under magnetic resonance imaging (MRI) procedure. With proper placement and selection of absorption material, one can alter the electromagnetic field and current distributions around and/or on medical devices so that the MRI RF field-induced heating can be reduced. The absorption-material-based RF heating reduction schemes are analyzed and validated. Numerical and experimental studies are conducted to illustrate the potentials of reducing the RF heating for external fixation devices. A design strategy based on response surface methodology is presented for material selection, and it is shown that absorption materials can significantly reduce the RF heating effects from 645 to 172 W/kg in terms of 1-g spatial-averaged SAR for the device under this investigation.

Description: In this paper, two models for the calculation of geomagnetically induced electric fields near the shoreline are compared. The first is an analytic model which requires the solution of an integral equation at each frequency, and the second is a simplified model that only requires Fourier transforms. The mechanism responsible for the differing results is determined, and it is suggested that one of the features of the analytic model should be included in the simplified model. This modification can be made without reducing the computational advantages of the second model. We also show the relative effect of the shoreline enhancement on the voltage impressed on cables for two different ground conductivities.

Description: For radiation source locating above a ground plane, its far field can be predicted by only the magnetic near field through the method proposed in this paper. This method applies the finite element method to get the equivalent current sources from the tangential magnetic near fields. With the equivalent current sources, the far-field radiation can be calculated based on Huygens's principle and image theory. The magnetic near field is scanned on a Huygens's surface that encloses the source with its ground. In this paper, this Huygens's surface was first proposed as a five-surface cube on the ground. Then, the Huygens's surface was further simplified by using four lines instead of four side walls to make the proposed method easier in regards to practical near-field scanning. Several numerical examples were tested to validate the proposed method. In addition, the proposed method was validated experimentally by using a patch antenna. The performance of using only the top plane near fields was also investigated and discussed. By using only the magnetic near fields on the simplified Huygens's surface, the proposed method significantly saves measurement time and cost while also retaining good far-field prediction.

Description: The difference of the partial self-inductance of a single conductor is determined between two extremes of the frequency range: at dc and at HF (infinite frequency). They are first calculated separately for a finite large length. Both contain the same logarithm(length) singularity, but this disappears in their difference, which only involves the logarithm of the ratio of the equivalent radius and the geometrical mean distance. We have applied this to some common conductor cross sections: circle, ellipse, rectangle, and diamond and to the limit of zero thickness of these cross sections. In the latter case, a general expression is derived.

Description: In a power inverter configuration with pull-up and pull-down transistors, ringing that occurs on the high-to-low and low-to-high transitions can be used to track aging or degradation of the transistors and potentially predict failures. Changes in a transistor's equivalent resistance and capacitance can affect the frequency and damping factor of the characteristic ringing detected on the inverter's output. In this paper, the matrix pencil method is used to locate the poles associated with this ringing, and detect shifts in position that indicate transistor degradation.

Description: In this paper, a quick and efficient approach is proposed to estimate in vivo RF-induced heating from small medical implants under MRI procedure. An efficient methodology is developed to correlate the incident electric field to the induced temperature rise for stents of arbitrary shapes. A 10-cm-long titanium rod and a 6-cm-long intestine stent are used as examples to validate the approach under in vitro testing conditions. In vivo temperature rise estimations are then performed on an anatomically corrected adult male model. Numerical and experimental studies demonstrate the efficiency and accuracy of the proposed method.

Description: As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18-MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup, including parallel and twisted pair harnesses, is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the failure level with the error of less than 20% in parallel harness case and around 30% in the twisted pair case.

Description: A hybrid approach is proposed to signal integrity analysis of trace and vias in plate pair with an infinitely large dimension. By using the domain decomposition method, trace domain and via domain are divided from the plate domain. Each individual domain of via and trace structure is modeled by the 3-D full-wave tool HFSS as a multimode network composed of TEM mode waveguide ports at top/bottom antipad interfaces and vertical lumped ports on the segmentation interfaces. The plate domain is dominated by TM Z0 modes and network parameters are solved by boundary integral method. Connection of network of each domain enforces the field continuity conditions along the segmentation interfaces and yields the final S parameter of trace and via as well as trace/via to trace/via coupling. Once the via pattern and trace routing are determined, the coupling can be efficiently modeled by the proposed hybrid approach and the layouts of via structures and trace routing in a plate pair are efficiently optimized.

Description: A fully operational 4G long-term evolution (LTE) base station is tested in a reverberation chamber to analyze its performance in the presence of a multipath environment, typical of wireless and vehicular communications. Transmission quality parameters are measured ranging from the empty chamber situation (very rich multipath channel) to a very high loading condition to mitigate multipath. In that way, both outdoor and indoor propagation are accounted for. A large attenuation is inserted between the transmitter and the antenna to reduce the signal received by the user to real-life values encountered in both outdoor and indoor environments. In these scenarios, operators may choose to transmit a constant power spectral density throughout all LTE spectrum, or to increase the energy of control channels at the expense of data channels in order to enforce transmission and provide better quality to the user, especially in poor radio conditions. This is called “power boosting,” and its effect is analyzed in this paper.

Description: Cage connectors for optical subassembly I/O modules have been identified as one of the main coupling paths in an optical link at the front-end of switches and routers. In the study presented herein, the simulation model used to study electromagnetic interference coupling physics and mitigation of the optical cage connector was corroborated by comparing the measured and simulated results for the total radiated power (TRP). Currents on the adjacent ground references to the differential signal conductors caused half-wave resonant peaks in the TRP response in the frequency range of 4–18 GHz. At frequencies from 18 to 28 GHz, both full-wave simulation and analytical formulas indicate that the radiation results primarily from the currents on the signal traces. The radiation from the optical cage connector was suppressed with absorbing materials, and the coupling path was verified, together with the optical cage and module enclosure.

Description: Electromagnetic radiation at a production printed circuit board (PCB) midplane connector is studied in this paper. A highly detailed simulation model is constructed and corroborated by comparing measured and simulated results, for both mixed-mode S-parameters and total radiated power, which is measured in a reverberation chamber and over-the-air anechoic chamber. The radiation loss in the production connector is a small fraction of the total loss. Common-mode antenna current is used to understand the radiation physics.

Description: The new era of cognitive computing brings forth the grand challenge of developing systems capable of processing massive amounts of noisy multisensory data. This type of intelligent computing poses a set of constraints, including real-time operation, low-power consumption and scalability, which require a radical departure from conventional system design. Brain-inspired architectures offer tremendous promise in this area. To this end, we developed TrueNorth, a 65 mW real-time neurosynaptic processor that implements a non-von Neumann, low-power, highly-parallel, scalable, and defect-tolerant architecture. With 4096 neurosynaptic cores, the TrueNorth chip contains 1 million digital neurons and 256 million synapses tightly interconnected by an event-driven routing infrastructure. The fully digital 5.4 billion transistor implementation leverages existing CMOS scaling trends, while ensuring one-to-one correspondence between hardware and software. With such aggressive design metrics and the TrueNorth architecture breaking path with prevailing architectures, it is clear that conventional computer-aided design (CAD) tools could not be used for the design. As a result, we developed a novel design methodology that includes mixed asynchronous–synchronous circuits and a complete tool flow for building an event-driven, low-power neurosynaptic chip. The TrueNorth chip is fully configurable in terms of connectivity and neural parameters to allow custom configurations for a wide range of cognitive and sensory perception applications. To reduce the system’s communication energy, we have adapted existing application-agnostic very large-scale integration CAD placement tools for mapping logical neural networks to the physical neurosynaptic core locations on the TrueNorth chips. With that, we have successfully demonstrated the use of TrueNorth-based systems in multiple applications, including visual object recognition, with higher performance and orders of magnitude lower- power consumption than the same algorithms run on von Neumann architectures. The TrueNorth chip and its tool flow serve as building blocks for future cognitive systems, and give designers an opportunity to develop novel brain-inspired architectures and systems based on the knowledge obtained from this paper.

Description: Provides a listing of board members, committee members and society officers.

Description: Many commercial systems in the embedded space have shown weakness against power analysis-based side-channel attacks in recent years. Random masking is a commonly used technique for removing the statistical dependency between the sensitive data and the side-channel information. However, the process of designing masking countermeasures is both labor intensive and error prone. Furthermore, there is a lack of formal methods for quantifying the actual strength of a countermeasure implementation. Security design errors may therefore go undetected until the side-channel leakage is physically measured and evaluated. We show a better solution based on static analysis of C source code. We introduce the new notion of quantitative masking strength (QMS) to estimate the amount of information leakage from software through side channels. Once the user has identified the sensitive variables, the QMS can be automatically computed from the source code of a countermeasure implementation. Our experiments, based on measurement on real devices, show that the QMS accurately reflects the side-channel resistance of the software implementation.

Description: Currently available electronic design automation tools for design space exploration of solid state drives (SSDs) are not able to assess: 1) the device architecture inefficiencies; 2) architecture overdesign for a target performance; and 3) performance degradation caused by the disk usage. These tools feature either an overly high abstraction modeling strategy or lack the required flexibility to perform design exploration. To overcome these problems, this paper proposes SSDExplorer, a tool for fine-grained yet reasonably fast design space exploration of different SSD architectures highlighting possible bottlenecks. To prove its accuracy SSDExplorer has been validated with two real SSDs. SSDExplorer efficiency has been assessed by evaluating the impact of the NAND flash read retry algorithm impact on the SSD performance as a function of its internal architecture.

Description: Radiation-induced soft errors have become a key challenge in advanced commercial electronic components and systems. We present the results of a soft error rate (SER) analysis of an embedded processor. Our SER analysis platform accurately models generation, propagation, and masking effects starting from a technology response model derived using TCAD simulations at the device level all the way to application masking. The platform employs a combination of accurate models at the device level, analytical error propagation at gate level, and fault emulation at the architecture/application level to provide the detailed contribution of each component (flip-flops, combinational gates, and SRAMs) to the overall SER. At each stage in the modeling hierarchy, an appropriate level of abstraction is used to propagate the effect of errors to the next higher level. Unlike previous studies which are based on very simple test chips, analyzing the entire processor gives more insight into the relative contributions of combinational and sequential SER. The results of this analysis can assist circuit designers to adopt effective hardening techniques to reduce the overall SER while meeting the required power and performance constraints.

Description: To improve the efficiency of direct solution methods in SPICE-accurate integrated circuit (IC) simulations, preconditioned iterative solution techniques have been widely studied in the past decades. However, it is still an extremely challenging task to develop robust yet efficient general-purpose preconditioning methods that can deal with various types of large-scale IC problems. In this paper, based on recent graph sparsification research we propose circuit-oriented general-purpose support-circuit preconditioning (GPSCP) methods to dramatically improve the sparse matrix solution time and reduce the memory cost during SPICE-accurate IC simulations. By sparsifying the Laplacian matrix extracted from the original circuit network using graph sparsification techniques, general-purpose support circuits can be efficiently leveraged as preconditioners for solving large Jacobian matrices through Krylov-subspace iterations. Additionally, a performance model-guided graph sparsification framework is proposed to help automatically build nearly-optimal GPSCP solvers. Our experiment results for a variety of large-scale IC designs show that the proposed preconditioning techniques can achieve up to $18 {times }$ runtime speedups and $7 {times }$ memory reduction in DC and transient simulations when compared to state-of-the-art direct solution methods.

Description: Electron-beam (e-beam) lithography has long been employed for mask writing but the write time is increasing due to the escalating mask pattern complexity. Besides, e-beam direct write is being pursued as an alternative solution for chip production in the sub-22 nm regime. To improve the throughput of e-beam lithography, character projection method is commonly employed and a critical problem is to pack as many useful characters as possible onto the stencil. In this paper, we consider three enhancements in packed stencil design over previous works. First, the fact that the pattern of a character can be located anywhere within its enclosing projection region is exploited to facilitate flexible blank space sharing. Second, the use of multiple shaping apertures with different sizes is explored. Third, the use of overlapping shots for printing some characters is investigated. For the packed stencil design problem with flexible blank space sharing and multiple shaping apertures, two dynamic programming-based algorithms are proposed, one allows overlapping shots and the other does not. Experimental results show that the proposed enhancement and the associated algorithms can significantly reduce the total shot count and hence improve the throughput of e-beam lithography.

Description: This paper proposes an efficient algorithm that maximizes performance under power constraints and is applicable in the general context of traditional dynamic voltage/frequency (V/P) scaling, or core heterogeneity and emerging dynamic micro-architectural adaptation. Performance maximization in these scenarios can be essentially viewed as mapping application threads to appropriate core states that have various power/performance characteristics. Such problems are formulated as a generic 0-1 integer linear program (ILP). The proposed algorithm is an iterative heuristic-based solution. Compared with an optimal solution generated by commercial ILP solver, the proposed algorithm produces results less than 1% away from optimum on average, with more than two orders of magnitude improvement in runtime. The algorithm can be brought online for hundred-core heterogeneous systems as it scales to systems comprised of 256 cores with less than 1 ms in overhead in worst cases. The intrinsic history awareness also provides flexibility to control cost induced by switching V/F pairs, migrating threads across cores, or tuning on/off micro-architectural resources. 1 A villainous son of Poseidon in Greek mythology who forces travelers to fit into his bed by stretching their bodies or cutting off their legs (adapted from Merriam-Webster).

Description: Graphics processing units (GPUs) have become ubiquitous for general purpose applications due to their tremendous computing power. Initially, GPUs only employ scratchpad memory as on-chip memory. Though scratchpad memory benefits many applications, it is not ideal for those general purpose applications with irregular memory accesses. Hence, GPU vendors have introduced caches in conjunction with scratchpad memory in the recent generations of GPUs. The caches on GPUs are highly configurable. The programmer or compiler can explicitly control cache access or bypass for global load instructions. This highly configurable feature of GPU caches opens up the opportunities for optimizing the cache performance. In this paper, we propose an efficient compiler framework for cache bypassing on GPUs. Our objective is to efficiently utilize the configurable cache and improve the overall performance for general purpose GPU applications. In order to achieve this goal, we first characterize GPU cache utilization and develop performance metrics to estimate the cache reuses and memory traffic. Next, we present efficient algorithms that judiciously select global load instructions for cache access or bypass. Finally, we present techniques to explore the unified cache and shared memory design space. We integrate our techniques into an automatic compiler framework that leverages parallel thread execution instruction set architecture to enable cache bypassing for GPUs. Experiments evaluation on NVIDIA GTX680 using a variety of applications demonstrates that compared to cache-all and bypass-all solutions, our techniques improve the performance from 4.6% to 13.1% for 16 KB L1 cache.

Description: Nonvolatile memory (NVM) has many benefits compared to the traditional static RAM, such as improved reliability and reduced power consumption, but it has long write latency and limited write endurance. Scratchpad memory (SPM) is software-managed small on-chip memory for improving system performance and predicability. We consider SPM based on spin-transfer torque RAM, a type of NVM with high performance and good endurance. We present algorithms for allocating data variables to SPM and distribute write activity evenly in the SPM address space, in order to achieve wear-leveling and prolong the lifetime of NVM. We present two optimization algorithms for minimizing system CPU utilization subject to NVM lifetime constraints: 1) an optimal algorithm based on ILP and 2) an efficient heuristic algorithm that can obtain close-to-optimal solutions.

Description: Finite field arithmetic operations have been traditionally used in different applications ranging from error control coding to cryptographic computations. Among these computations are normal basis multiplications and exponentiations which are utilized in efficient applications due to their advantageous characteristics and the fact that squaring (and subsequent powering by two) of elements can be obtained with no hardware complexity. In this paper, we present 2-D decomposition systolic-oriented algorithms to develop systolic structures for digit-level Gaussian normal basis multiplication and exponentiation over $ {GF}({2}^{m})$ . The proposed high-performance architectures are suitable for a number of applications, e.g., architectures for elliptic curve Diffie–Hellman key agreement scheme in cryptography. The results of the benchmark of efficiency, performance, and implementation metrics of such architectures through a 65-nm application-specific integrated circuit platform confirm high-performance structures for the multiplication and exponentiation architectures presented in this paper are suitable for high-speed architectures, including cryptographic applications.

Description: This paper introduces a new methodology for pipeline synthesis with applications to data flow high-level system design. The pipeline synthesis is applied to dataflow programs whose operators are translated into graphs and dependencies relations that are then processed for the pipeline architecture optimization. For each pipeline-stage time, a minimal number of pipeline stages are first determined and then an optimal assignment of operators to stages is generated with the objective of minimizing the total pipeline register size. The obtained “optimal” pipeline schedule is automatically transformed back into a dataflow program that can be synthesized to efficient hardware implementations. Two new pipeline scheduling: “least cost search branch and bound” and a heuristic technique have been developed. The first algorithm yields global optimum solutions for middle size designs, whereas the second one generates close-to-optimal solutions for large designs. Experimental results on FPGA designs show that the total pipeline register size gain in a range up to $4.68 {times } $ can be achieved. The new algorithms overcome the known downward and upward direction dataflow graph traversal algorithms concerning the amount of pipeline register size by up to 100% on average.

Description: In analog designs, the most widely adopted layout practice to improve matching is the symmetrical common-centroid placement. However, this arrangement cannot be obtained in general. In this paper, it is shown that there are asymmetrical placements with a common centroid which are also immune to process gradients and suitable for designs where a symmetrical layout is not possible. In addition, this paper proposes an automated method, based on a standard simulated annealing framework, to arrange fully-integrated capacitors in a layout to improve their matching.

Description: With the steady growth of chip complexity and shrinking feature size, multiple challenges are emerging for transistor level circuit simulation. Compact SPICE models are a fundamental part of circuit verification, serving as a bridge between the semiconductor design and foundry. It is also an integral part of SPICE simulators, which directly affects tool performance and therefore design schedule. While the advanced 3-D technology nodes deliver superior level of scalability, simulation cost is rapidly increasing due to the computational complexity introduced by device model equations and the number of iterations required for numerical methods. In this paper, an efficient solution is proposed to reduce the computational cost associated with UC Berkeley BSIM-CMG device model evaluation, by applying robust Verilog compiler and computer algebra techniques to the device model equations. As a result of this implementation, simulation time reduction is up to 72% for complex blocks of the latest generation processor design.

Description: The hardware Trojan threat has motivated development of Trojan detection schemes at all stages of the integrated circuit (IC) lifecycle. While the majority of existing schemes focus on ICs at test-time, there are many unique advantages offered by post-deployment/run-time Trojan detection. However, run-time approaches have been underutilized with prior work highlighting the challenges of implementing them with limited hardware resources. In this paper, we propose three innovative low-overhead approaches for run-time Trojan detection which exploit the thermal sensors already available in many modern systems to detect deviations in power/thermal profiles caused by Trojan activation. The first one is a local sensor-based approach that uses information from thermal sensors together with hypothesis testing to make a decision. The second one is a global approach that exploits correlation between sensors and maintains track of the ICs thermal profile using a Kalman filter (KF). The third approach incorporates leakage power into the system dynamic model and apply extended KF (EKF) to track ICs thermal profile. Simulation results using state-of-the-art tools on ten publicly available Trojan benchmarks verify that all three proposed approaches can detect active Trojans quickly and with few false positives. Among three approaches, EKF is flawless in terms of the ten benchmarks tested but would require the most overhead.

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Description: This paper provides qualitative and quantitative values for the received interference power at the antenna ports of automotive radars as well as the probability of their occurrence for actual and future, not yet measurable traffic scenarios on main roads. The influence of the environment, the road traffic behavior, and the radar penetration rate for a defined antenna configuration can be observed. The basis for the analyses are ray-tracing based simulations in order to achieve adequate predictions for the received power levels due to multipaths. The results show that for a radar penetration rate of 100%, the difference between the strongest overall incoherent received interference power level and the level that is received in 90% of the time is up to 7 dB, dependent on the antenna placement and the environment.

Description: Electric drive systems are going to be the future of the automotive industry. Electromagnetic compatibility (EMC) issues and challenges arise with its growing entry into modern cars. This contribution provides an overview of the field dominating disturbance currents of an automotive high-voltage (HV) power inverter within an electric drive system. In order to minimize the cost and time needed for EMC measurements and engineering, a precompliance measurement method is introduced and applied to the inverter's setup. The method presented allows the calculation of radiated emissions, according to CISPR 25, needed during the development process without the need for an expensive anechoic chamber. Transfer functions in combination with measured disturbance currents on the attached HV harnesses are used to obtain a cost-efficient estimation of the radiated emissions occurring during a component test. Its theory is discussed and demonstrated using a derived model. The method is verified using a rudimentary test setup, which represents a distributed system, and is later validated by the active electric drive system test setup introduced. Examinations of repeatability and reproducibility of disturbance current measurements as well as applied EMC counter measures complete the contribution.

Description: In this paper, a coplanar symmetrical meander line structure is presented, and an equivalent circuit model is proposed to allow estimation of its electrical characteristics based on numerical modeling. The parasitic couplings in the proposed structure are considerably different from those of a simple meander line with a ground structure below it. Analysis and derivation of inductive and capacitive couplings and of resistance in the effective frequency band are addressed in detail, and the effects of geometrical parameters on the electrical characteristics are also demonstrated. The validity of the proposed equivalent circuit model is verified by both commercial electromagnetic simulator and measurement of the scattering parameters in the frequency domain, as well as of the reflected and transmitted waveforms in the time domain. Because the proposed model is easily coded, and takes little time to compute the parameters, it is very useful in the design of inductance and capacitance in circuits on substrate, which can be used for the design of time-delay elements and stop band filters in power delivery lines.

Description: In this paper, a new formulation in the time domain of the Cooray–Rubinstein expression is presented. This new formulation overcomes the problems related to the previous formulation: The Dirac pulse contained in the kernel of the previous formulation is extracted, making the numerical treatment easier and more accurate.

Description: Lightning electromagnetic pulse (LEMP) is a severe threat to sensitive electronic devices installed in buildings. To protect these devices from LEMP effects, the evaluation of the electromagnetic fields inside of the building is required. Although numerous studies have been devoted to the analysis of these fields stemming from direct and indirect lightning strikes, no thorough study on the analysis of the electromagnetic environment inside a building with layered reinforcing bars has been presented in the past. In this paper, using the 3-D finite-difference time-domain method, we present a systematic analysis of the electromagnetic field inside a full-scale building associated with direct and nearby lightning strikes, taking into account the presence of reinforced concrete, to evaluate the effect of the structure of the reinforced concrete on the lightning electromagnetic fields.

Description: In this paper, lightning-induced voltages on multiconductor lines with surge arresters and pole transformers have been computed using the 3-D finite-difference time-domain method. This method uses a subgrid model, in which spatial discretization is fine (cell side length is 0.5 m) in the vicinity of overhead wires and coarse (cell side length is 5 m) in the rest of the computational domain. In the simulations, four-conductor lines with surge arresters and pole transformers are considered. The 1-cm-radius overhead conductors are represented by placing a wire having an equivalent radius of about 0.12 m (≈ 0.23 × 0.5 m) in the center of an artificial rectangular prism having a cross-sectional area of 1 m × 1 m (2 cells × 2 cells) and the modified (relative to air) constitutive parameters: lower electric permittivity and higher magnetic permeability. The computed lightning-induced voltage waveforms agree reasonably well with the corresponding ones measured in the small-scale experiment of Piantini et al. (2007).

Description: The random coupling model (RCM) and Baum–Liu–Tesche EM topology have been well developed to describe the statistical fluctuation of the scattering and impedance matrices of wave-chaotic metallic-enclosed cavity, and the interaction of interconnected networks of complicated enclosures, respectively. In this paper, a stochastic approach that combines these two methods is tested and verified on a network of wave-chaotic metallic cavities, and induced voltage derived by this method is also compared with other methods.

Description: This paper introduces an equivalent circuit model for through silicon vias including the nonlinear effect of metal–oxide–semiconductor capacitance. This nonlinear effect is combined to the frequency-dependent via resistance and inductance, as well as capacitance and conductance of the silicon substrate for a transient analysis. The impact of frequency-dependent RLCG parameters and the nonlinear depletion capacitance on signal propagation, crosstalk and eye diagram is studied using the proposed equivalent circuit model.

Description: The design of robust receivers in environments with strong impulsive noise may be challenging due to their high-amplitude events and their rare but nonnegligible occurrence. In substation environments, these impulsive noises are predominant. They are induced by corona discharges such as electrical arcs or partial discharges in the air. The emitted radiations can occupy a wide range of frequencies typically reaching a few gigahertz with very high amplitude. In this paper, we develop a generalized model of impulsive electromagnetic interference induced by corona discharges for wireless channels. Radiations emitted by these sources are generally transient impulses, their occurrences follow cyclostationary process, due to their generation by an alternative current. In this model, we both take into account the physical mechanism of these discharges and the induced electromagnetic radiations. Experimental results validate the approach in terms of first- and second-order statistics such as amplitudes, interarrival time, occurrences, and power spectrum densities of impulsive transient noise.

Description: A simple and efficient analytical method has been developed for predicting the electromagnetic field coupling with a lossless transmission line (TL) located in a rectangular enclosure. The metallic enclosure is excited by an internal electrical short dipole or monopole source. The electric fields generated inside the rectangular enclosure and excited by some simple sources are calculated by using the electric-type dyadic Green's function. Our approach combines, on one hand, a lumped-pi circuit model of TL and, on the other hand, the Agrawal coupling model. A simple equivalent circuit has been derived which can give prediction for the coupling between the cavity field and the TL. This method is computationally less intensive compared to other numerical methods to solve such a problem. The analytical results have been successfully compared over a wide frequency band with the finite-difference time domain and experimental results carried out in different combinations of source and line position.

Description: A SPICE model for the twisted-wire pair with uniform twists in free space is proposed in this paper, which is capable of calculating the transient terminal response of the twisted-wire pair terminated with nonlinear loads in the presence of a transient plane wave illumination. The model differs from its counterpart for a straight-wire pair in that an extra convolution is included in the source terms, which can be calculated efficiently by the recursive convolution method. For the sake of convenience, the derivation of the model is made in the frequency domain on the basis of the transmission-line theory. The resultant expressions are compared with the outcome of the method of moments, showing that the transmission-line model can be applied to the twisted-wire pair with loose twists. Furthermore, the low-frequency coupling properties and resonant peak of the twisted-wire pairs are investigated according to the derived approximate formulae. Based on the frequency-domain results, a SPICE model for the twisted-wire pair is proposed in the time domain before it is verified and applied to the twisted-wire pair terminated with nonlinear loads.

Description: A plane wave integral representation for fields in reverberation chambers has been found useful for the idealized case of well-stirred fields. The representation satisfies Maxwell's equations, and the statistical properties of the fields are obtained by letting the angular spectrum be a random variable with appropriate statistical properties. This representation yields the expected idealized ensemble (stirring) averages, in particular, spatial uniformity and isotropy. The purpose of this letter is to show that this representation is unique in that no other field representation will yield these desired ensemble averages.

Description: A simple and straightforward method to estimate the maximal instantaneous voltage peak during switching operations in resonant structures is presented. It is based on the time-domain analysis of an elementary RLC circuit as a model for such systems. For short pulses, a very simple relation is obtained, independent of the pulse shape. For slow excitations, the noise amplitude is safely estimated solely by the slew rate. Pulses with arbitrary length and shape are approximately treated by a trapezoid with effective width and rise time, for which an accurate solution is derived. The approach is extended to current pulse trains. Several validation examples demonstrate the applicability and versatility of the developed estimation formulas.

Description: This letter describes the design and implementation of a wideband radio frequency-baseband multiplexer. This device makes it possible to superimpose radio frequency noise to a functional baseband signal with controlled and repeatable transfer characteristics. The baseband path has a measured dc—380 $mathrm{M}$ $mathrm{Hz}$ bandwidth, while the radio frequency path (up to 1  $mathrm{W}$ ) has a 150 $mathrm{k}$ $mathrm{Hz}$ $text{-}$ 5 $mathrm{G}$ $mathrm{Hz}$ bandwidth. This multiplexer can be used for electromagnetic conducted immunity testing of digital and mixed-signal devices.

Description: Terrestrial trunked radio (TETRA) is a digital radio standard that was developed to meet the needs of professional mobile radio systems. TETRA is vulnerable to intentional electromagnetic interference (EMI) because of the wireless link. The EMI can easily be front door coupled to the base station via the antenna and cause a denial-of-service of the communication. In this paper, the robustness of TETRA against front door coupled intentional EMI is investigated. Three different interfering mechanisms are discussed: damage of the receiver, saturation of the receiver, and masking the communication signal. The interference mechanisms are fundamentally different and needs to be addressed separately. We present two experimental methods to test the robustness of a base station receiver against different interference mechanisms. Results show that the analyzed TETRA base station is very robust against out-of-channel interference with moderate power levels. Intentional EMI is expected to be in-channel because an adversary will exploit the vulnerable frequencies, and this can disrupt TETRA communications.

Description: A previous paper mentioned that the international standard ISO 11452-4:2005 has given a requirement for the calibration fixture of current probe, i.e., the voltage standing wave ratio (VSWR) of the calibration fixture should be less than 1.2. Here is a comment about this.

Description: As nanometer technology advances, conventional optical proximity correction (OPC) that minimizes the edge placement error (EPE) at the nominal process condition alone often leads to poor process windows. To improve the mask printability across various process corners, process-window OPC optimizes EPE for multiple process corners, but often suffers long runtime, due to repeated lithographic simulations. This paper presents an efficient process variation (PV)-aware mask optimization framework, namely PVOPC, to simultaneously minimize EPE and PV band with fast convergence. The PVOPC framework includes EPE-sensitivity-driven dynamic fragmentation, PV-aware EPE modeling, and correction with three new EPE-converging techniques and a systematic subresolution-assisted feature insertion algorithm. Experimental results show that our approach efficiently achieves high-quality EPE and PV band results.

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Description: Binning after volume production is a widely accepted technique to classify fabricated integrated circuits (ICs) into different clusters depending on different degrees of specification compliance. This allows the manufacturer to sell nonoptimal devices at lower rates, so adapting to customer’s quality-price requirements. The binning procedure can be carried out by measuring every single circuit performances, but this approach is costly and time-consuming. On the contrary, if alternate measurements are used to characterize the bins, the procedure is considerably enhanced. In such a case, the specification bin boundaries become arbitrary shape regions due to the highly nonlinear mappings between the specifications space and the alternate measurements space. The binning strategy proposed in this paper functions with the same efficiency regardless of these shapes. The digital encoding of the bins in the alternate measurements space using octrees is the key idea of the proposal. The strategy has two phases: 1) the training phase and 2) the binning phase. In the training phase, the specification bins are encoded using octrees. This first phase requires sufficient samples of each class to generate the octree under realistic variations, but it only needs to be performed once. The binning phase corresponds to the actual production binning of the fabricated ICs. This is achieved by evaluating the alternate measurements in the previously generated octree. The binning phase is fast due to the inherent sparsity of the octree data structure. In order to illustrate the proposal, the method has been applied to a band-pass Butterworth filter considering three specification bins as a proof of concept. Successful simulation results are reported showing considerable advantages as compared to a support vector machine (SVM)-based classifier. Similar bin misclassifications are obtained with both methods, 1.68% using octrees and 1.83% using SVM, while binning time is $5times $ times faster using octrees than using the SVM-based classifier.

Description: With shrinking process technology, decreasing supply voltage, and increasing clock frequency, noise reduction becomes more and more crucial to the success of modern mixed-signal system-on-chip design. To eliminate the switching noise due to crosstalk coupling between analog and digital signals, it is essential to fully separate the routing paths of analog and digital nets when generating mixed-signal layouts. Different from previous works which cannot fully separate analog and digital routing paths, this paper presents a novel hierarchical deterministic mixed-signal layout synthesis approach with the separation of analog and digital signal paths for switching noise elimination. Experimental results based on a third-order $ {Sigma Delta }$ modulator show that the proposed approach can result in various layouts with separated analog and digital signal paths while achieving better signal-to-noise and distortion ratio, and overall performance specifications.

Description: Efficient performance modeling of today’s analog and mixed-signal circuits is an important yet challenging task, due to the high-dimensional variation space and expensive circuit simulation. In this paper, we propose a novel performance modeling algorithm that is referred to as Bayesian model fusion (BMF) to address this challenge. The key idea of BMF is to borrow the information collected from an early stage (e.g., schematic level) to facilitate efficient performance modeling at a late stage (e.g., post layout). Such a goal is achieved by statistically modeling the performance correlation between early and late stages through Bayesian inference. Furthermore, to make the proposed BMF method of practical utility, four implementation issues, including: 1) prior mapping; 2) missing prior knowledge; 3) fast solver; and 4) prior and hyper-parameter selection, are carefully considered in this paper. Two circuit examples designed in a commercial 32 nm CMOS silicon on insulator process demonstrate that the proposed BMF method achieves up to $9times $ runtime speed-up over the traditional modeling technique without surrendering any accuracy.

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Description: Layout-dependent effects (LDEs) have become a critical issue in modern analog and mixed-signal circuit designs. The three major sources of LDEs, well proximity, length of oxide diffusion, and oxide-to-oxide spacing, significantly affect the threshold voltage and mobility of devices in advanced technology nodes. In this paper, we propose the first work to consider the three major sources of LDEs during analog placement. We first transform the three LDE models into nonlinear analytical placement models. Then an LDE-aware analytical analog placement algorithm is presented to mitigate the influence of the LDEs while improving circuit performance. Experimental results show that our placement algorithm can effectively and efficiently reduce the LDE-induced variations and improve circuit performance.

Description: Reconfigurable digital filter is being widely used in applications such as communication and signal processing. Its performance, power consumption, and logic resource utilization are the major factors to be taken into consideration when designing the filters. This paper proposes a concise canonic signed digit coefficient grouping method aiming at reducing the number of common subexpressions (CSs). Further, we statistically analyze every CS occurance for numerous sorts of the finite-impulse response (FIR) filters and obtain characterization of the distribution behavior for all the possible CS patterns in a 16-bit coefficient. Thus, a novel processing element structure is proposed to form a medium-grain array for computationally efficient realization of reconfigurable FIR filter. The experiment results suggest such design implementations typically achieve 21% reduction in silicon area, 20% decrease in power consumption, and 14% improvement in operation speed in comparison to other conventional FIR architectures.

Description: Digital microfluidic biochips (DMFBs) are gaining increasing attention with promising applications for automating and miniaturizing laboratory procedures in biochemistry. In DMFBs, cross-contamination of droplets with different biomolecules is a major issue, which causes significant errors in bioassays. Washing operations are introduced to clean the cross-contamination spots. However, existing works have oversimplified assumptions on the washing behavior, which either assume infinite washing capacity, or ignore the routing conflicts between functional and washing droplets. This paper proposes the first integrated functional and washing droplet routing flow, which considers practical issues including the finite washing capacity constraint, and the routing conflicts between functional and washing droplets. Washing droplets of different sizes are also proposed to wash the congested cross-contamination spots. Effectiveness of the proposed method is validated by real-life biochemical applications.

Description: It is known that bus-oriented escape routing and area routing are necessary in a high-speed printed circuit board (PCB) design. In this paper, given a set of global routed buses in a high-speed PCB design, it is assumed that the routed nets in a single bus are represented as a bus-oriented net between two escaped boundary pins. Based on the construction of a virtual wall between two circuit components, the connection transformation of the given bus-oriented nets inside a closed region and the construction of a covering graph for the represented intervals, an iterative modified left-edge algorithm is proposed to minimize the number of the assigned layers and assign all the bus-oriented nets onto the available layers. Compared with Tsai’s algorithm, the experimental results show that our proposed algorithm reduces 15.0% of the layer number and 21.9% of CPU time for six tested examples on the average, respectively. Compared with Chin’s algorithm, the experimental results show that our proposed algorithm use less CPU time to reduce 15.0% of the layer number for six tested examples on the average.

Description: Provides a listing of the editors, board members, and current staff for this issue of the publication.

Description: Applications executed on multicore embedded systems interact with system software [such as the operating system (OS)] and hardware, leading to widely varying thermal profiles which accelerate some aging mechanisms, reducing the lifetime reliability. Effectively managing the temperature therefore requires: 1) autonomous detection of changes in application workload and 2) appropriate selection of control levers to manage thermal profiles of these workloads. In this paper, we propose a technique for workload change detection using density ratio-based statistical divergence between overlapping sliding windows of CPU performance statistics. This is integrated in a runtime approach for thermal management, which uses reinforcement learning to select workload-specific thermal control levers by sampling on-board thermal sensors. Identified control levers override the OSs native thread allocation decision and scale hardware voltage–frequency to improve average temperature, peak temperature, and thermal cycling. The proposed approach is validated through its implementation as a hierarchical runtime manager for Linux, with heuristic-based thread affinity selected from the upper hierarchy to reduce thermal cycling and learning-based voltage–frequency selected from the lower hierarchy to reduce average and peak temperatures. Experiments conducted with mobile, embedded, and high performance applications on ARM-based embedded systems demonstrate that the proposed approach increases workload change detection accuracy by an average ${3.4times }$ , reducing the average temperature by 4 °C–25 °C, peak temperature by 6 °C–24 °C, and thermal cycling by 7%–35% over state-of-the-art approaches.

Description: This paper proposes an efficient time-domain mixed potential integral equation (TD-MPIE) technique to analyze the penetrated transient electromagnetic field into a perforated rectangular metallic enclosure loaded with conducting objects. To this end, the surface equivalent principle is applied, and the fields in the interior and the exterior regions of the enclosure are formulated by using the time-domain cavity and free space Green's functions, respectively. Then, the governing TD-MPIE is derived by enforcing the continuity of the tangential magnetic and electric fields on the surface of the apertures and conducting loads inside the shield, respectively. The resultant time-domain equation is then solved by using the marching-on-in time scheme. Here, the spatial integrations and temporal convolutions are carried out analytically which eliminates the need to complicated numerical integration routines and remove the late time instability. In addition, an accelerated algorithm is proposed to scale down the computational complexity from $O(N_{rm mod } N_t^2 N_s^2)$ down to $O(N_{{rm mod}} N_t (log ^2 N_t + 2N_s))$ where $N_{{rm mod}}$ , $N_{t}$ and $N_{s}$ denote the total number of necessary modes inside the cavity, the number of time steps, and the spatial unknowns, respectively. The accuracy of the proposed technique is validated by comparing the simulated results with the well-known CST Microwave Studio time-domain solver, as well as the frequency-domain solution, and the measurements.

Description: Coupling between closely spaced wideband analog radio frequency integrated circuits can cause degradation in device performance. Methods for reducing the coupling between packages were tested, with a strong focus on maintaining manufacturability and minimizing any increase in coupling between structures within the package. Methods include the application of magnetic absorbing material or resistive sheets to the package surface and the inclusion of conductive vias in the package walls. Package modifications were tested from 5–40 GHz through both full-wave simulation and physical measurement. The best tradeoff in performance and manufacturability below 20 GHz was found using 250-Ω/sq. resistive sheets connected to the return plane with vias in the package corners, while above 20 GHz, the best tradeoff was found by covering the package with magnetic absorbing materials. The magnetic absorbing material can be embedded directly in the package polymer itself, allowing easy manufacture.

Description: A formula is derived for the plane wave shielding effectiveness of a spacecraft Faraday cage with a penetrating cable. The potentially disastrous effects of space radiation, corrosion, and thermal cycling are described.

Description: This paper presents the results of a radiated electromagnetic field due to lightning strike to a tall tower sitting on a mountainous terrain when considering both the first and subsequent return strokes. A cone-shaped ground with finite conductivity represents the mountainous terrain; and a cylindrical two-dimensional finite-difference time-domain (FDTD) scheme is used to determine the lightning-generated electromagnetic fields. The return stroke channel is modeled using the antenna theory model with fixed inductive loading which is appropriately incorporated into the FDTD algorithm. Simulation results are presented for different values of the cone angle and height, and for different values of the tower height. It is shown that when the first and subsequent return strokes hit a tower on a cone-shaped ground, the radiated electric and magnetic fields experience an enhancement in their amplitudes as compared to the case where the tower sits on a flat ground. Also, the current reflections from the tower base, influencing the current distribution along the tower and radiated electromagnetic field waveforms, depend on the cone angle and height, as well as the tower height.

Description: Near-threshold computing has emerged as a promising solution to significantly increase the energy efficiency of next-generation multicore systems. This paper evaluates and analyzes the behavior of dynamic voltage and frequency scaling for multicore systems operating under extended range: including near-threshold, nominal, and turbo modes. We adapt the model selection technique from machine learning to determine the relationship between performance and power. The theoretical results show that the resulting models satisfy convexity, which efficiently determines the optimal voltage/frequency operating points for: 1) minimizing energy consumption under throughput constraints or 2) maximizing throughput under a given power budget. We validate our models on FinFET-based chip-multiprocessors. Considering process variations (PVs), experimental results show that at 30% PV levels, our proposed method: 1) reduces energy consumption by 31.09% at iso-performance condition and 2) increases throughput by 11.46% at iso-power when compared with variation-agnostic nominal case.

Description: This paper presents two circuit models of the electromagnetic (EM) clamp defined in Standard IEC 61000-4-6 for conducted-immunity (CI) testing. First, a lumped-parameter circuit model is extracted from measurements of scattering parameters. This model is merely behavioral since it provides a valid representation of the EM clamp at external ports up to 1 GHz, whereas physical interpretation of the involved sources/impedances is possible under 10 MHz only. To extend physical insight at higher frequencies, a distributed-parameter circuit model is proposed, which is based on the description of the internal structure of the EM clamp as a three-conductor transmission line. Unknown model parameters (such as the magnetic permeability of ferrite rings) are identified by optimized fitting of ad hoc measurements. Both models are eventually validated by experiments performed in an idealized CI test setup. Several observations on the operating principles and features of the EM clamp are inferred from the two complementary modeling approaches.

Description: In this paper, we present an efficient and accurate approach to predict the shielding effectiveness (SE) of an enclosure with numerous small apertures, which involves two methods: the equivalent model of aperture array and waveguide equivalent circuit model. First, the equivalent model of aperture array is derived from the numerical simulation that simplifies the aperture array into a single aperture, then the equivalent single aperture's impedance is calculated and the equivalent circuit model is applied to calculate the SE of the enclosure. The result shows a better agreement with the measurement than the original waveguide equivalent circuit model. In comparison with aperture's admittance model, our method can be applied to the square, circular, and rectangular apertures with nonuniform small aperture distribution. The proposed method can also significantly reduce the simulation time and improve the efficiency of simulation compared with the generalized modal method of moments and CST. Finally, we discuss the applicability of this method.

Description: This study reports the simple, inexpensive, and in situ deposition of polyaniline (PANI) on polyacrylonitrile (PAN) woven fabric with the reactive ink-jet printing technique aimed at the manufacturing of multilayered electromagnetic interference (EMI) shields. The electrical characteristics of fabric samples are measured by the van der Pauw method. The surface resistance value of the treated fabrics steadily decreases when the number of the PANI-printed layers increases and reaches the lowest surface resistance value of 20 Ω/sq. The PANI-printed PAN structures are characterized and evaluated in terms of their electromagnetic shielding effectiveness (SE), absorption (insertion loss), and reflection characteristics. These characteristics are determined by means of a network analyzer with a frequency range from 2.6 to 18 GHz. One layer of PAN fabric ink-jet printed with conducting PANI, which gives a surface weight equal to ca 20 g/m 2 , shows a SE of ca 5 dB. However, tripling the surface weight of PANI on PAN fabric shows a SE of ca. 12 dB, whereas a fivefold increase in the PANI surface weight shows a SE of ca. 22 dB. The equivalent analog circuit model with an approximation approach for predicting the SE, reflection coefficient, and insertion loss for the cases, which are not experimentally tested is proposed.

Description: Recently, large-scale diode grids have received much attention with regard to spatial electromagnetic (EM) field protection of electronic systems. The distributed nature of diode grids and the large number of elements (usually hundreds or even more) pose a challenging problem for numerical modeling. In this paper, a hybrid field-circuit simulation combining the method of moments and a causal convolution technique is proposed for transient analysis of such diode grids. Emphasis is put on the treatment of causality and passivity violations caused by incorporation of a frequency-dependent distributed multiport network into a circuit solver. Specifically, when considering a large-scale multiport network, an enhanced causal correction approach with minor passivity violations is proposed to improve the simulation accuracy and stability. For validation, $text{3} times text{3}$ and $text{9} times text{9}$ grid arrays excited by incident fields are investigated, and the results provided by the proposed method are compared to the simulation results of commercial software. Furthermore, an EM application example with a $text{15} times text{15}$ diode grid is demonstrated. The simulations show a field-intensity-dependent transmission of diode grids which is suitable, e.g., for EM protection of communication systems with sensitive electronics.

Description: During the last years, the large hadron collider (LHC), the most powerful particle accelerator in the world, has been running at CERN in Geneva, Switzerland. It includes four large high-energy experiments and the compact muon solenoid (CMS) is one of them. The electronic read-out for the CMS experiment is designed to process signals in the range of $mu$ A-mA and digitize them synchronously at 40 MHz. Parts of these electronic systems are located inside of a uniform magnetic field of 4 T and operate under particle radiation. These characteristics have forced us to analyze, propose, and conduct electromagnetic compatibility (EMC) tests on the electronic equipment before integrating it into the detector. This paper presents the description and analysis of the first EMC plan and tests that were applied to a high-energy physics experiment before the installation and commissioning of the electronics system.