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  • Artikel  (14)
  • fault simulation  (13)
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  • Elektrotechnik, Elektronik, Nachrichtentechnik  (14)
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  • Artikel  (14)
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  • 1
    Digitale Medien
    Digitale Medien
    Fault simulation for mixed-signal systems (1996)
    Springer
    Journal of electronic testing 8 (1996), S. 143-152 
    Details
    ISSN: 1573-0727
    Schlagwort(e): fault simulation ; mixed-signal systems ; bridging faults
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract This paper proposes a solution to achieve the global fault simulation for mixed-signal systems. Fault models for analog defects are introduced. Short-circuit defects, involving two digital nodes or involving a digital and an analog node, are also supported. Short-circuit modelling is achieved by a local analog simulation and by means of new mixed-signal models suggested for CMOS devices. Using a commercially available mixed-signal simulator, we built surrounding tools to automate the fault simulation. By processing the circuit description files, they allow generating and reducing a fault list and controlling the fault simulation, Simulation results are also processed in order to produce an exhaustivity report and a selection of the best test vectors.
    Materialart: Digitale Medien
    URL: http://dx.doi.org/10.1007/BF02341820
    Standort Signatur Erwartet Verfügbarkeit
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  • 2
    Digitale Medien
    Digitale Medien
    A unified approach for fault simulation of linear mixed-signal circuits (1996)
    Springer
    Journal of electronic testing 9 (1996), S. 29-41 
    Details
    ISSN: 1573-0727
    Schlagwort(e): testing ; mixed-signal ; fault simulation ; arithmetic distance
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract The rapidly evolving role of analog signal processing has spawned off a variety of mixed-signal circuit applications. The integration of the analog and digital circuits has created a lot of concerns in testing these devices. This paper presents an efficient unified fault simulation platform for mixed-signal circuits while accounting for the imprecision in analog signals. While the classical stuck-at fault model is used for the digital part, faults in the analog circuit cover catastrophic as well as parametric defects in the passive and active components. A unified framework is achieved by combining a discretized representation of the analog circuit with the Z-domain representation of the digital part. Due to the imprecise nature of analog signals, an arithmetic distance based fault detection criterion and a statistical measure of digital fault coverage are proposed.
    Materialart: Digitale Medien
    URL: http://dx.doi.org/10.1007/BF00137563
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  • 3
    Digitale Medien
    Digitale Medien
    Fault Modeling and Simulation Using VHDL-AMS (1998)
    Springer
    Analog integrated circuits and signal processing 16 (1998), S. 141-155 
    Details
    ISSN: 1573-1979
    Schlagwort(e): analog simulation ; analog test ; fault simulation ; fault modeling ; analog VHDL
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract Fault simulation is an accepted part of the test generation procedure for digital circuits. With complex analog and mixed-signal integrated circuits, such techniques must now be extended. Analog simulation is slow and fault simulation can be prohibitively expensive because of the large number of potential faults. We describe how the number of faults to be simulated in an analog circuit can be reduced by fault collapsing, and how the simulation time can be reduced by behavioral modeling of fault-free and faulty circuit blocks. These behavioral models can be implemented in SPICE or in VHDL-AMS and we discuss the merits of each approach. VHDL-AMS does potentially offer advantages in tackling this problem, but there are a number of computational difficulties to be overcome.
    Materialart: Digitale Medien
    URL: http://dx.doi.org/10.1023/A:1008267723105
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  • 4
    Digitale Medien
    Digitale Medien
    Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits (1998)
    Springer
    Journal of electronic testing 12 (1998), S. 239-254 
    Details
    ISSN: 1573-0727
    Schlagwort(e): delay test ; fault simulation ; path-delay faults ; transition faults ; statistical fault analysis
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract We present a technique to statistically estimate path-delay fault coverage for synchronous sequential circuits. We perform fault-free simulation using a multivalue algebra and accumulate signal transition statistics, from which we calculate controllabilities of all signals and sensitization probabilities for all gates and flip-flops. We use a rated clock testing model where all time frames operate at the rated clock. We obtain path observabilities either by enumerating paths in the all-paths method, or by a nonenumerative method considering only the longest paths. The path-delay fault detectability is the product of observabilities of signals on paths from primary inputs (PIs) or pseudo-primary inputs (PPIs) to primary outputs (POs) or pseudo-primary outputs (PPOs), and the controllability on the corresponding PI or PPI. We use the optimistic update rule of Bose et al. for updating latches during logic simulation. When compared with exact fault simulation, the average absolute deviation in our statistical fault coverage estimation technique is 1.23% and the very worst absolute deviation was 6.59%. On average, our method accelerates delay fault coverage computation four times over an exact path delay fault simulator.
    Materialart: Digitale Medien
    URL: http://dx.doi.org/10.1023/A:1008228817698
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  • 5
    Digitale Medien
    Digitale Medien
    On Non-Statistical Techniques for Fast Fault Coverage Estimation (1999)
    Springer
    Journal of electronic testing 15 (1999), S. 239-254 
    Details
    ISSN: 1573-0727
    Schlagwort(e): fault coverage estimation ; fault simulation ; test generation ; tolerance ; hyperactivity reduction
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract We present fast, dynamic fault coverage estimation techniques for sequential circuits that achieve high degrees of accuracy and significant reductions in the number of injected faults and faulty-event evaluations. In the proposed techniques, we dynamically reduce injection of hyperactive faults as well as faults whose effects never propagate to a flip-flop or primary output. Suppression and over-specification of potential fault-effects are also investigated to reduce faulty-event evaluations. Experiments show that our methods give very accurate estimates with frequently greater speedups than the sampling techniques for most circuits. Most significantly, the proposed techniques can be combined with the sampling approach to obtain speedups comparable to small sample sizes and retain estimation accuracy of large fault samples.
    Materialart: Digitale Medien
    URL: http://dx.doi.org/10.1023/A:1008332723359
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  • 6
    Digitale Medien
    Digitale Medien
    Hybrid Fault Simulation for Synchronous Sequential Circuits (1999)
    Springer
    Journal of electronic testing 15 (1999), S. 219-238 
    Details
    ISSN: 1573-0727
    Schlagwort(e): fault simulation ; symbolic simulation ; SOT ; MOT ; BDD
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract We present a fault simulator for synchronous sequential circuits that combines the efficiency of three-valued logic simulation with the exactness of a symbolic approach. The simulator is hybrid in the sense that three different modes of operation—three-valued, symbolic and mixed—are supported. We demonstrate how an automatic switching between the modes depending on the computational resources and the properties of the circuit under test can be realized, thus trading off time/space for accuracy of the computation. Furthermore, besides the usual Single Observation Time Test Strategy (SOT) for the evaluation of the fault coverage, the simulator supports evaluation according to the more general Multiple Observation Time Test Strategy (MOT). Numerous experiments are given to demonstrate the feasibility and efficiency of our approach. In particular, it is shown that, at the expense of a reasonable time penalty, the exactness of the fault coverage computation can be improved even for the largest benchmark functions.
    Materialart: Digitale Medien
    URL: http://dx.doi.org/10.1023/A:1008376522451
    Standort Signatur Erwartet Verfügbarkeit
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  • 7
    Digitale Medien
    Digitale Medien
    A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes (1995)
    Springer
    Journal of electronic testing 6 (1995), S. 75-84 
    Details
    ISSN: 1573-0727
    Schlagwort(e): Built-in self-test ; compact testing ; fault coverage ; fault simulation ; signature analysis ; multiple signature analysis
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract In this article, a strategy based on the use of intermediate signatures is proposed that enables the exact fault coverage of compact testing schemes to be determined in a feasible computation time. Two models to predict fault simulation time, a fault simulator dependent and independent model, are developed and used by a dynamic programming based algorithm to find the optimal scheduling of the signatures with respect to the total simulation time. Simulation results for both models are then presented demonstrating the feasibility of the proposed strategy.
    Materialart: Digitale Medien
    URL: http://dx.doi.org/10.1007/BF00993131
    Standort Signatur Erwartet Verfügbarkeit
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  • 8
    Digitale Medien
    Digitale Medien
    Symbolic Handling of Bridging Fault Effects (1997)
    Springer
    Journal of electronic testing 10 (1997), S. 271-276 
    Details
    ISSN: 1573-0727
    Schlagwort(e): fault simulation ; bridging faults ; binary decision diagrams (BDDs)
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract This paper introduces a new fault simulation methodology based onsymbolic handling of fault effects. Boolean variables are related tofaulty signals, and fault effects are propagated by computing gateoutput expressions by means of BDDs. The proposed technique canhandle in a single simulation step such faults as resistive bridges,that exhibit a parametric behavior, thus requiring more simulationswith conventional techniques.
    Materialart: Digitale Medien
    URL: http://dx.doi.org/10.1023/A:1008223826585
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  • 9
    Digitale Medien
    Digitale Medien
    Workload Distribution in Fault Simulation (1997)
    Springer
    Journal of electronic testing 10 (1997), S. 277-282 
    Details
    ISSN: 1573-0727
    Schlagwort(e): fault simulation ; logic simulation ; parallel simulation ; parallelization ; workload distribution
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract Simulation at the gate level is computationally very expensive.Parallel processing is one technique to reduce simulation time.Possessing knowledge of the distribution of computational activity insimulation can aid in parallelizing it efficiently. We present a newcharacterization of the distribution of the computational workload infault simulation. An empirical analysis shows that the workloaddistribution is circuit specific, and is largely independent of thevector set being simulated. An inexpensive method to predict theworkload distribution is also discussed.
    Materialart: Digitale Medien
    URL: http://dx.doi.org/10.1023/A:1008275810655
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  • 10
    Digitale Medien
    Digitale Medien
    Parallel sequence fault simulation for synchronous sequential circuits (1996)
    Springer
    Journal of electronic testing 9 (1996), S. 267-277 
    Details
    ISSN: 1573-0727
    Schlagwort(e): logic simulation ; fault simulation ; parallel sequence simulation
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract A novel parallel sequence fault simulation (PSF) algorithm for synchronous sequential circuits is presented. The algorithm successfully extend the parallel pattern method for combinational circuits to sequential circuits by proposing a multiple-pass mechanism to overcome the state dependency in sequential circuits. The fault simulation is performed in parallel by partitioning the entire sequence into subsequences of equal length. Furthermore, techniques are developed to minimize the number of simulation passes. Notably, two compact counters, C x and C d , are proposed to faciliate the early stabilization detection of faulty circuit simulation with minimum space overhead. The experimental results on the benchmark circuits show that the speedup ratio over a serial sequence fault simulator based on ROOFS is 9.16 on average for pseudo random vectors. The parallel sequence algorithm of PSF is especially adaptable to parallel and distributed simulation which exploits sequence partition.
    Materialart: Digitale Medien
    URL: http://dx.doi.org/10.1007/BF00134691
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