ALBERT

Beschreibung: A field-programmable gate array (FPGA) on a single lightweight, low-power integrated-circuit chip has been developed to implement an azimuth pre-filter (AzPF) for a synthetic-aperture radar (SAR) system. The AzPF is needed to enable more efficient use of data-transmission and data-processing resources: In broad terms, the AzPF reduces the volume of SAR data by effectively reducing the azimuth resolution, without loss of range resolution, during times when end users are willing to accept lower azimuth resolution as the price of rapid access to SAR imagery. The data-reduction factor is selectable at a decimation factor, M, of 2, 4, 8, 16, or 32 so that users can trade resolution against processing and transmission delays. In principle, azimuth filtering could be performed in the frequency domain by use of fast-Fourier-transform processors. However, in the AzPF, azimuth filtering is performed in the time domain by use of finite-impulse-response filters. The reason for choosing the time-domain approach over the frequency-domain approach is that the time-domain approach demands less memory and a lower memory-access rate. The AzPF operates on the raw digitized SAR data. The AzPF includes a digital in-phase/quadrature (I/Q) demodulator. In general, an I/Q demodulator effects a complex down-conversion of its input signal followed by low-pass filtering, which eliminates undesired sidebands. In the AzPF case, the I/Q demodulator takes offset video range echo data to the complex baseband domain, ensuring preservation of signal phase through the azimuth pre-filtering process. In general, in an SAR I/Q demodulator, the intermediate frequency (fI) is chosen to be a quarter of the range-sampling frequency and the pulse-repetition frequency (fPR) is chosen to be a multiple of fI. The AzPF also includes a polyphase spatial-domain pre-filter comprising four weighted integrate-and-dump filters with programmable decimation factors and overlapping phases. To prevent aliasing of signals, the bandwidth of the AzPF is made 80 percent of fPR/M. The choice of four as the number of overlapping phases is justified by prior research in which it was shown that a filter of length 4M can effect an acceptable transfer function. The figure depicts prototype hardware comprising the AzPF and ancillary electronic circuits. The hardware was found to satisfy performance requirements in real-time tests at a sampling rate of 100 MHz.

Beschreibung: Figure 1 shows a single-stage monolithic microwave integrated circuit (MMIC) power amplifier in which the gain element is a double-heterojunction bipolar transistor (DHBT) connected in common-base configuration. This amplifier, which has been demonstrated to function well at a frequency of 172 GHz, is part of a continuing effort to develop compact, efficient amplifiers for scientific instrumentation, wide-band communication systems, and radar systems that will operate at frequencies up to and beyond 180 GHz. The transistor is fabricated from a layered structure formed by molecular beam epitaxy in the InP/InGaAs material system. A highly doped InGaAs base layer and a collector layer are fabricated from the layered structure in a triple mesa process. The transistor includes two separate emitter fingers, each having dimensions of 0.8 by 12 m. The common-base configuration was chosen for its high maximum stable gain in the frequency band of interest. The input-matching network is designed for high bandwidth. The output of the transistor is matched to a load line for maximum saturated output power under large-signal conditions, rather than being matched for maximum gain under small-signal conditions. In a test at a frequency of 172 GHz, the amplifier was found to generate an output power of 7.5 mW, with approximately 5 dB of large-signal gain (see Figure 2). Moreover, the amplifier exhibited a peak small-signal gain of 7 dB at a frequency of 176 GHz. This performance of this MMIC single-stage amplifier containing only a single transistor represents a significant advance in the state of the art, in that it rivals the 170-GHz performance of a prior MMIC three-stage, four-transistor amplifier. [The prior amplifier was reported in "MMIC HEMT Power Amplifier for 140 to 170 GHz" (NPO-30127), NASA Tech Briefs, Vol. 27, No. 11 (November 2003), page 49.] This amplifier is the first heterojunction- bipolar-transistor (HBT) amplifier built for medium power operation in this frequency band. The performance of the amplifier as measured in the aforementioned tests suggests that InP/InGaAs HBTs may be superior to high-electron-mobility (HEMT) transistors in that the HBTs may offer more gain per stage and more output power per transistor.