Publication Date:
2015-11-05
Description:
A hybrid P/N channel junctionless (JL) thin-film transistor (TFT) with back-gate bias (V bg ) has been demonstrated. By applying negative bias of V bg = −8 V in gate length of 50 nm shows excellent SS ( 10 8 ), and high V th modulation. The increased I on simultaneously decreased I off via negative V bg is attributed to smaller surface E-field at ON-state, significantly reducing the impact on interface traps and thinner effective channel thickness at OFF-state, improving gate controllability. Hence, hybrid P/N JL-TFT with V bg is a promising for low power circuit, power management, and System-on-Chip applications.
Print ISSN:
0003-6951
Electronic ISSN:
1077-3118
Topics:
Physics
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