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  • 1
    Electronic Resource
    Electronic Resource
    Testing of programmable analog neural network chips (1994)
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 8 (1994), S. 267-282 
    Details
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Artificial neural network chips can achieve high-speed performance in solving complex computational problems for signal and information processing applications. These chips contain regular circuit units such as synapse matrices that interconnect linear arrays of input and output neurons. The neurons and synapses may be implemented in an analog or digital design style. Although the neural processing has some degree of fault tolerance, a significant percentage of processing defects can result in catastrophic failure of the neural network processors. Systematic testing of these arrays of circuitry is of great importance in order to assure the quality and reliability of VLSI neural network processor chips. The proposed testing method consists of parametric test and behavioral test. Two programmable analog neural chips have been designed and fabricated. The systematic approach used to test the chips is described, and measurement results on parametric test are presented.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF02106451
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  • 2
    Electronic Resource
    Electronic Resource
    A VLSI neuroprocessor for image restoration using analog computing-based systolic architecture (1993)
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 5 (1993), S. 185-199 
    Details
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract An analog computing-based systolic architecture which employs multiple neuroprocessors for high-speed early vision processing is presented. For a two-dimensional image, parallel processing is performed in the row direction and pipelined processing is performed in the column direction. The mixed analog/digital design approach is suitable for implementation of electronic neural systems. Local data computation is executed by analog circuitry to achieve full parallelism and to minimize power dissipation. Inter-processor communication is carried out in the digital format to maintain strong signal strength across the chip boundary and to achieve direct scalability in neural network size. For demonstration purposes, a compact and efficient VLSI neural chip that includes multiple neuroprocessors for high-speed digital image restoration is designed. Measured results of the programmable synapse, and statistical distribution of measured synapse conductances are presented. Based on these results, system-level analyses at 8-bit resolution are conducted. A 8.0×6.0-mm 2 chip from a 1.2-µm CMOS technology can accommodate 5 neuroprocessors and the speed-up factor over the Sun-4/75 SPARC workstation is around 450. This chip achieves 18 Giga connections per second.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF01581295
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  • 3
    Electronic Resource
    Electronic Resource
    A mixed-signal VLSI competitive neuroprocessor for video motion detection (1993)
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 6 (1993), S. 57-66 
    Details
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract VLSI design of a competitive neural network for video motion detection is presented. Massively parallel neurocomputing is performed by compact and efficient neuroprocessors. Local data transfer between the neuroprocessors is carried out by using an analog point-to-point interconnection scheme, while global data communication between the host computer and neuroprocessors is achieved through a digital common bus. Experimental results of the analog circuit blocks and system-level analysis on a sequence of real-world images are also presented.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF01581959
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  • 4
    Electronic Resource
    Electronic Resource
    Automatic layout synthesis of analog ICs using circuit recognition and constraint analysis techniques (1991)
    Springer
    Analog integrated circuits and signal processing 1 (1991), S. 75-87 
    Details
    ISSN: 1573-1979
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A systematic method for automatic layout synthesis of analog integrated circuit modules is presented. This method uses analog circuit recognition and critical net analysis techniques to derive proper layout constraints for analog circuit performance optimization. These layout constraints are analyzed and prioritized according to the recognized analog circuit topologies and classified net sensitivities. The weighted constraints are then used to drive the physical layout generation process to obtain a high-quality custom circuit layout. An efficient, constraint-driven analog floorplanning technique based on a zone-sensitivity partitioning algorithm is specially developed to generate a slicing floorplan incorporating the layout constraints. This layout synthesis approach has three key advantages. First, it can produce a satisfactory analog circuit performance with negligible degradation due to the layout-introduced parasitic effects. Second, it allows a complete automation for netlist-to-layout synthesis so that the layout tool can be used by VLSI system designers. Finally, this method is quite general and can be applied to handle a wide variety of analog circuits. Experimental results in CMOS operational amplifiers and a comparator are presented.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF02151027
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  • 5
    Electronic Resource
    Electronic Resource
    Architecture and Design of 1-D Enhanced Cellular Neural Network Processors for Signal Detection (1998)
    Springer
    Analog integrated circuits and signal processing 15 (1998), S. 277-290 
    Details
    ISSN: 1573-1979
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract One-dimensional cellular array processor architecture and design for neural-based partial response (PR) signal detection are presented. Analog parallel computing approaches have many attractive advantages in achieving low power, low cost, and faster processing speed by its uniquely coupled parallel and distributed processing nature. In this paper, we describe the maximum likelihood sequence estimation (MLSE) algorithm for PR signals, the enhanced Cellular Neural Network (CNN) processor array architecture to realize the detection algorithm, and system performance evaluation. Analytical models and simulations on a design example of the detector have been employed to demonstrate the advantages of this scalable VLSI architecture. A processing rate of 265 Mbps was achieved for a prototype detector on a silicon area of 5.14 mm by 5.81 mm is a 1.2 µm CMOS technology. The processing rate can be beyond 1Gbps if it is implemented in the same amount of silicon area by using 0.5 µm CMOS technology. Such promising results clearly demonstrate the ability to meet the needs in future high speed data communication by VLSI realization of maximum likelihood sequence detectors based on the enhanced cellular neural network paradigm.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008270330503
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  • 6
    Electronic Resource
    Electronic Resource
    A nonvolatile analog neural memory using floating-gate MOS transistors (1992)
    Springer
    Analog integrated circuits and signal processing 2 (1992), S. 19-25 
    Details
    ISSN: 1573-1979
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Simple floating-gate transistors fabricated by a conventional double-polysilicon process show excellent programming and charge-retention characteristics. A five-transistor synapse cell achieves 8-bit resolution and at least 6-bit accuracy for analog neural computation. It occupies 67 μm×73 μm in a 2-μm CMOS process and can retain charge accuracy for over 25 years.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00249249
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  • 7
    Electronic Resource
    Electronic Resource
    Programmable-weight building blocks for analog VLSI neural network processors (1996)
    Springer
    Analog integrated circuits and signal processing 9 (1996), S. 215-230 
    Details
    ISSN: 1573-1979
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Although the neural network paradigms have the intrinsic potential for parallel operations, a traditional computer cannot fully exploit it because of the serial hardware configuration. By using the analog circuit design approach, a large amount of parallel functional units can be realized in a small silicon area. In addition, appropriate accuracy requirements for neural operation can be satisfied. Components for a general-purpose neural chip have been designed and fabricated. Dynamically adjusted weight value storage provides programmable capability. Possible reconfigurable schemes for a general-purpose neural chip are also presented. Test of the prototype neural chip has been successfully conducted and an expected result has been achieved.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00194906
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  • 8
    Electronic Resource
    Electronic Resource
    Behavioral simulation of densely-connected analog cellular array processors for high-performance computing (1996)
    Springer
    Analog integrated circuits and signal processing 10 (1996), S. 77-88 
    Details
    ISSN: 1573-1979
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract The analog cellular neural network (CNN) model is a powerful parallel processing paradigm in solving many scientific and engineering problems. The network consists of densely-connected analog computing cells. Various applications can be accomplished by changing the local interconnection strengths, which are also called coefficient templates. The behavioral simulator could help designers not only gain insight on the system operations, but also optimize the hardware-software co-design characteristics. An unique feature of this simulator is the hardware annealing capability which provides an efficient method of finding globally optimal solutions. This paper first gives an overview of the cellular network paradigm, and then discusses the nonlinear integration techniques and related partition issues, previous work on the simulator and our own simulation environment. Selective simulation results are also presented at the end.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00713980
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  • 9
    Electronic Resource
    Electronic Resource
    A Unified Approach to Submicron DC MOS Transistor Modeling for Low-Voltage ICs (1997)
    Springer
    Analog integrated circuits and signal processing 12 (1997), S. 107-118 
    Details
    ISSN: 1573-1979
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A unified single-equation approach for the MOS transistordrain current modeling for energy-efficient submicron MOS circuitsis presented. Instead of three sets of separate equations forthe triode, saturation, and weak inversion regions, only a continuousexpression which is valid to describe the behavior of drain currentand the derivatives in all operation regions can be realizedby using a combination of hyperbola, sigmoid, and interpolationmethods. The model expression can predict accurate results forthe current, output conductance, and transconductance with continuousand smooth characteristics. The simulation results agree wellwith experimental data.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008212908346
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  • 10
    Electronic Resource
    Electronic Resource
    Explicit geometry dependence of MOS transistor parameters by the pseudoboundary method (1992)
    Springer
    Analog integrated circuits and signal processing 2 (1992), S. 105-115 
    Details
    ISSN: 1573-1979
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract The pseudoboundary method is an engineering technique to extend the use of a single parameter set over the entire geometric design space for VLSI circuits. The technique eliminates adverse effects, such as negative output conductance, by clamping the evaluation of geometric dependence terms at the systematically determined boundaries of a primary region. The use of this technique is essential for accurate simulation of analog and digital circuits as well as prediction of circuit performance using next-generation submicron VLSI fabrication technologies. Results demonstrating the effectiveness of the technique using the widely accepted Berkeley short-channel IGFET model (BSIM) are presented, with data from transistors of different geometries ranging from 0.5 to 70 μm.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00142411
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