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  • 1
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    GFI - EASY PC GRAPHICS (1994)
    In:  Other Sources
    Details
    Publication Date: 2011-08-24
    Description: Easy PC Graphics (GFI) is a graphical plot program that permits data to be easily and flexibly plotted. Data is input in a standard format which allows easy data entry and evaluation. Multiple dependent axes are also supported. The program may either be run in a stand alone mode or be embedded in the user's own software. Automatic scaling is built in for several logarithmic and decibel scales. New scales are easily incorporated into the code through the use of object-oriented programming techniques. For the autoscale routines and the actual plotting code, data is not retrieved directly from a file, but a "method" delivers the data, performing scaling as appropriate. Each object (variable) has state information which selects its own scaling. GFI is written in Turbo Pascal version 6.0 for IBM PC compatible computers running MS-DOS. The source code will only compile properly with the Turbo Pascal v. 6.0 or v. 7.0 compilers; however, an executable is provided on the distribution disk. This executable requires at least 64K of RAM and DOS 3.1 or higher, as well as an HP LaserJet printer to print output plots. The standard distribution medium for this program is one 5.25 inch 360K MS-DOS format diskette. The contents of the diskette are compressed using the PKWARE archiving tools. The utility to unarchive the files, PKUNZIP.EXE, is included. An electronic copy of the documentation is provided on the distribution medium in ASCII format. GFI was developed in 1993.
    Keywords: COMPUTER PROGRAMMING AND SOFTWARE
    Type: GSC-13592
    Format: text
    Location Call Number Expected Availability
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  • 2
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    SRAM Based Re-programmable FPGA for Space Applications (1999)
    In:  CASI
    Details
    Publication Date: 2013-08-29
    Description: An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 micrometers CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor de-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I(sub CC)) measured indicates a device tolerance of approximately 50krad(Si).
    Keywords: Computer Programming and Software
    Format: application/pdf
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    NASA TECHNICAL REPORTS
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