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  • 1
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    In:  CASI
    Publication Date: 2013-08-31
    Description: Inversion layer (IL) Metal Oxide Semiconductor (MOS) solar cells were fabricated. The fabrication technique and problems are discussed. A plan for modeling IL cells is presented. Future work in this area is addressed.
    Keywords: ENERGY PRODUCTION AND CONVERSION
    Type: NASA. Marshall Space Flight Center Research Reports: 1986 NASA(ASEE Summer Faculty Fellowship Program; 21 p
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  • 2
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    In:  CASI
    Publication Date: 2013-08-31
    Description: A group of inversion layer MOS solar cells has been fabricated. The highest value of open-circuit voltage obtained for the cells is 0.568V. One of the cells has produced a short-circuit current of 79.6 mA and an open-circuit voltage of 0.54V. It is estimated that the actual area AMO efficiency of this cell is 6.6 percent with an assumed value of 0.75 for its fill factor. Efforts made for fabricating an IL/MOS cell with reasonable efficiencies are reported. Future work for 4 sq cm IL cells and 25 sq cm IL cells is discussed.
    Keywords: ENERGY PRODUCTION AND CONVERSION
    Type: NASA. Marshall Space Flight Center, Research Reports: 1987 NASA(ASEE Summer Faculty Fellowship Program; 16 p
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  • 3
    Publication Date: 2019-06-28
    Description: Many inversion-layer metal-insulator-semiconductor (IL/MIS) solar cells have been fabricated. There are around eighteen 1 cm(exp 2) IL/MIS solar cells which have efficiencies greater than 7%. There are only about three 19 cm(exp 2) IL/MIS cells which have efficiencies greater than 4%. The more accurate control of the thickness of the thin layer of oxide between aluminum and silicon of the MIS contacts has been achieved. A lot of effort and progress have been made in this area. A comprehensive model for MIS contacts under dark conditions has been developed that covers a wide range of parameters. It has been applied to MIS solar cells. One of the main advantages of these models is the prediction of the range of the thin oxide thickness versus the maximum efficiencies of the MIS solar cells. This is particularly important when the thickness is increased to 25 A. This study is very useful for our investigation of the IL/MIS solar cells. The two-dimensional numerical model for the IL/MIS solar cells has been tried to develop and the results are presented in this report.
    Keywords: Energy Production and Conversion
    Type: NASA-CR-201956 , NAS 1.26:201956
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  • 4
    Publication Date: 2018-06-12
    Description: All present ferroelectric transistors have been made on the micrometer scale. Existing models of these devices do not take into account effects of nanoscale ferroelectric transistors. Understanding the characteristics of these nanoscale devices is important in developing a strategy for building and using future devices. This paper takes an existing microscale ferroelectric field effect transistor (FFET) model and adds effects that become important at a nanoscale level, including electron velocity saturation and direct tunneling. The new model analyzed FFETs ranging in length from 40,000 nanometers to 4 nanometers and ferroelectric thickness form 200 nanometers to 1 nanometer. The results show that FFETs can operate on the nanoscale but have some undesirable characteristics at very small dimensions.
    Keywords: Electronics and Electrical Engineering
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  • 5
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    In:  CASI
    Publication Date: 2019-06-28
    Description: Many inversion layer metal-insulator-semiconductor (IL/MIS) solar cells have been fabricated. As of today, the best cell fabricated by us has a 9.138 percent AMO efficiency, with FF = 0.641, V(sub OC) = 0.557 V, and I(sub SC) = 26.9 micro A. Efforts made for fabricating an IL/MOS solar cell with reasonable efficiencies are reported. The more accurate control of the thickness of the thin layer of oxide between aluminum and silicon of the MIS contacts has been achieved by using two different process methods. Comparison of these two different thin oxide processings is reported. The effects of annealing time of the sample are discussed. The range of the resistivity of the substrates used in the IL cell fabrication is experimentally estimated. Theoretical study of the MIS contacts under dark conditions is addressed.
    Keywords: ENERGY PRODUCTION AND CONVERSION
    Type: NASA-CR-190212 , NAS 1.26:190212
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  • 6
    Publication Date: 2019-07-17
    Description: A pair of electronic models has been developed of a Ferroelectric Field Effect transistor. These models can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The models use the Schmitt trigger circuit as a basis for their design. One model uses bipolar junction transistors and one uses MOSFET's. Each model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current from each model has similar values to an actual FFET that was measured experimentally. T'he input and o Output resistance in the models are also similar to that of the FFET. The models are valid for all frequencies below RF levels. No attempt was made to model the high frequency characteristics of the FFET. Each model can be used to design circuits using FFET's with standard electrical simulation packages. These circuits can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The models consist of only standard electrical components, such as BJT's, MOSFET's, diodes, resistors, and capacitors. Each model is compared to the experimental data measured from an actual FFET.
    Keywords: Electronics and Electrical Engineering
    Type: Integrated Ferroelectrics; Mar 11, 2001; Colorado Springs, CO; United States
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  • 7
    Publication Date: 2019-07-13
    Description: The ferroelectric channel in a Metal-Ferroelectric-Semiconductor Field Effect Transistor (MFSFET) can partially change its polarization when the gate voltage near the polarization threshold voltage. This causes the MFSFET Drain current to change with repeated pulses of the same gate voltage near the polarization threshold voltage. A previously developed model [11, based on the Fermi-Dirac function, assumed that for a given gate voltage and channel polarization, a sin-le Drain current value would be generated. A study has been done to characterize the effects of partial polarization on the Drain current of a MFSFET. These effects have been described mathematically and these equations have been incorporated into a more comprehensive mathematical model of the MFSFET. The model takes into account the hysteresis nature of the MFSFET and the time dependent decay as well as the effects of partial polarization. This model defines the Drain current based on calculating the degree of polarization from previous gate pulses, the present Gate voltage, and the amount of time since the last Gate volta-e pulse.
    Keywords: Electronics and Electrical Engineering
    Type: Integrated Ferroelectrics; Mar 07, 1999; Colorado Springs, CO; United States
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  • 8
    Publication Date: 2019-07-13
    Description: A two dimensional numerical model of the inversion layer metal insulator semiconductor (IL/MIS) solar cell is proposed by using the finite element method. The two-dimensional current flow in the device is taken into account in this model. The electrostatic potential distribution, the electron concentration distribution, and the hole concentration distribution for different terminal voltages are simulated. The results of simple calculation are presented. The existing problems for this model are addressed. Future work is proposed. The MIS structures are studied and some of the results are reported.
    Keywords: ENERGY PRODUCTION AND CONVERSION
    Type: NASA-CR-187875 , NAS 1.26:187875
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  • 9
    Publication Date: 2019-07-18
    Description: A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.
    Keywords: Electronics and Electrical Engineering
    Type: 14th International Symposium on Integrated Ferroelectrics; Mar 12, 2003; Colordao Springs, CO; United States
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  • 10
    Publication Date: 2019-07-18
    Description: An electronic simulation model has been developed of a ferroelectric field effect transistor (FFET). This model can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The model uses a previously developed algorithm that incorporates partial polarization as a basis for the design. The model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current has values matching actual FFET's, which were measured experimentally. The input and output resistance in the model is similar to that of the FFET. The model is valid for all frequencies below RF levels. A variety of different ferroelectric material characteristics can be modeled. The model can be used to design circuits using FFET'S with standard electrical simulation packages. The circuit can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The model is a drop in library that integrates seamlessly into a SPICE simulation. A comparison is made between the model and experimental data measured from an actual FFET.
    Keywords: Electronics and Electrical Engineering
    Type: International Joint Conference on the Applications of Ferroelectrics 2002; May 28, 2002; Nara; Japan
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