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  • 1
    Publication Date: 2008-08-25
    Description: Efficiency of solar cell power systems outside the earths atmosphere
    Keywords: COMMUNICATIONS
    Type: JPL-TR-32-259
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  • 2
    Publication Date: 2011-08-24
    Description: A picosec pulsed dye laser beam was at selected wavelengths successfully used to simulate heavy-ion single-event effects (SEEs) in negative channel NMOS DRAMs. A DRAM was used to develop the test technique because bit-mapping capability and previous heavy-ion upset data were available. The present analysis is the first to establish such a correlation between laser and heavy-ion data for devices, such as the NMOS DRAM, where charge collection is dominated by long-range diffusion, which is controlled by carrier density at remote distances from a depletion region. In the latter case, penetration depth is an important parameter and is included in the present analysis. A single-pulse picosecond dye laser beam (1.5 microns diameter) focused onto a single cell component can upset a single memory cell; clusters of memory cell upsets (multiple errors) were observed when the laser energy was increased above the threshold energy. The multiple errors were analyzed as a function of the bias voltage and total energy of a single pulse. A diffusion model to distinguish the multiple upsets from the laser-induced charge agreed well with previously reported heavy ion data.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Solid-State Electronics (ISSN 0038-1101); 35; 7; p. 905-912.
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  • 3
    Publication Date: 2011-08-19
    Description: Charged-particle interactions in microelectronic circuit chips (integrated circuits) present a particularly insidious problem for solid-state electronic systems due to the generation of soft errors or single-particle event upset (SEU) by either cosmic rays or other radiation sources. Particle accelerators are used to provide both light and heavy ions in order to assess the propensity of integrated circuit chips for SEU. Critical aspects of this assessment involve the ability to analytically model SEU for the prediction of error rates in known radiation environments. In order to accurately model SEU, the measurement and prediction of energy deposition in the form of an electron-hole plasma generated along an ion track is of paramount importance. This requires the use of accelerators which allow for ease in both energy control (change of energy) and change of ion species. This and other aspects of ion-beam control and diagnostics (e.g., uniformity and flux) are of critical concern for the experimental verification of theoretical SEU models.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Nuclear Instruments and Methods in Physics Research (ISSN 0168-9002); B10; 11, 1; 757-762
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  • 4
    Publication Date: 2011-08-19
    Description: A detailed experimental investigation of single-event upset (SEU) in static RAM (SRAM) chips fabricated using a family of high-performance NMOS (HMOS) depletion-mode-load process technologies, has been done. Empirical SEU models have been developed with the aid of heavy-ion data obtained with a three-stage tandem van de Graaff accelerator. The results of this work demonstrate a method by which SEU may be empirically modeled in NMOS integrated circuits.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Transactions on Nuclear Science (ISSN 0018-9499); NS-33; 1581-158
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  • 5
    Publication Date: 2011-08-19
    Description: Tests showed that bipolar chips in the attitude control computer of the Galileo spacecraft would likely cause catastrophic mission failure due to single particle upset. This paper describes the design and testing of CMOS replacements which are speed compatible with the bipolar parts and are immune to upset by 165-MeV krypton ions.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Transactions on Nuclear Science (ISSN 0018-9499); NS-32; 4159-416
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  • 6
    Publication Date: 2011-08-19
    Description: Results are given of SEU measurements on 256K dynamic RAMs with on-chip error correction. They are claimed to be the first ever reported. A (12/8) Hamming error-correcting code was incorporated in the layout. Physical separation of the bits in each code word was used to guard against multiple bits being disrupted in any given word. Significant reduction in observed errors is reported.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Transactions on Nuclear Science (ISSN 0018-9499); NS-34; 1310-131
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  • 7
    Publication Date: 2011-08-19
    Description: Modeling of SEU has been done in a CMOS static RAM containing 1-micron-channel-length transistors fabricated from a p-well epilayer process using both circuit-simulation and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator. Experimental evidence for a novel SEU mode in an ON n-channel device is presented.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Transactions on Nuclear Science (ISSN 0018-9499); NS-34; 1292-129
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  • 8
    Publication Date: 2011-08-19
    Description: A 256K DRAM has been used to study the lateral transport of charge (electron-hole pairs) induced by direct ionization from heavy-ion tracks in an IC. The qualitative charge transport has been simulated using a two-dimensional numerical code in cylindrical coordinates. The experimental bit-map data clearly show the manifestation of lateral charge transport in the creation of adjacent multiple-bit errors from a single heavy-ion track. The heavy-ion data further demonstrate the occurrence of multiple-bit errors from single ion tracks with sufficient stopping power. The qualitative numerical simulation results suggest that electric-field-funnel-aided (drift) collection accounts for single error generated by an ion passing through a charge-collecting junction, while multiple errors from a single ion track are due to lateral diffusion of ion-generated charge.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Transactions on Nuclear Science (ISSN 0018-9499); 35; 1644-164
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  • 9
    Publication Date: 2011-08-19
    Description: The spread of charge induced by an ion track in an integrated circuit and its subsequent collection at sensitive nodal junctions can cause multiple-bit errors. The authors have experimentally and analytically investigated this phenomenon using a 256-kb dynamic random-access memory (DRAM). The effects of different charge-transport mechanisms are illustrated, and two classes of ion-track multiple-bit error clusters are identified. It is demonstrated that ion tracks that hit a junction can affect the lateral spread of charge, depending on the nature of the pull-up load on the junction being hit. Ion tracks that do not hit a junction allow the nearly uninhibited lateral spread of charge.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Transactions on Nuclear Science (ISSN 0018-9499); 36; 2267-227
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  • 10
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    In:  Other Sources
    Publication Date: 2011-08-18
    Description: The results of work done on the quantitative characterization of single-event upset (SEU) in bipolar random-access memories (RAMs) have been obtained through computer simulation of SEU in RAM cells that contain circuit models for bipolar transistors. The models include current generators that emulate the charge collected from ion tracks. The computer simulation results are compared with test data obtained from a RAM in a bipolar microprocessor chip. This methodology is applicable to other bipolar integrated circuit constructions in addition to RAM cells.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: IEEE Transactions on Nuclear Science (ISSN 0018-9499); NS-30; 4540-454
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