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  • 1
    Electronic Resource
    Electronic Resource
    Rapid prototyping methodology for multiprocessor implementation of digital signal processing systems (1995)
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 11 (1995), S. 21-34 
    Details
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A methodology for the hierarchical partitioning and mapping of digital signal processing (DSP) tasks to heterogeneous local cluster based network of very large scale integration (VLSI) processors is presented. The goal is to achieve rapid prototyping of VLSI DSP systems. The high level partitioning issues of DSP task graphs and the proposed metrics to guide the partitioning process are described in this paper. Partitioning tominimize power inefficiency in the DSP system is one important metric addressed by this work, since low power signal processing is paramount to new portable and high density multi-chip module (MCM) DSP systems. The application of theRatio Cut Partitioning approach to DSP graphs is explained. We illustrate our results with examples and show how the final partitions vary depending upon the target architecture to meet rapid prototyping requirements. We compare our approach with known techniques and show that it works much better for our target applications.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF02106821
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    Paper (German National Licenses)
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  • 2
    Electronic Resource
    Electronic Resource
    Power dissipation of VLSI array processing systems (1992)
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 4 (1992), S. 199-212 
    Details
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract The Power Factor Approximation (PFA) power estimation method is reviewed and applied to VLSI array processing systems. The power dissipation of 1, 2, and 3 dimensional algorithms implemented on linear, hexagonal, and cubic processor arrays is investigated. Closed form equations are developed which show how the overall power dissipation is influenced by an algorithm's size and dimensionality, the target array processor's size and dimensionality, and the adopted partitioning strategy. The power estimation methods developed in this paper can be applied in the early phases of VLSI algorithm/architecture design, selection, and partitionment. The power dissipation of a matrix-matrix multiplication operation is estimated as an example application.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00925122
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    Paper (German National Licenses)
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  • 3
    Electronic Resource
    Electronic Resource
    Dynamic adaptation of quantization thresholds for soft-decision viterbi decoding with a reinforcement learning neural network (1993)
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 6 (1993), S. 77-84 
    Details
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Two reinforcement learning neural network architectures which enhance the performance of a soft-decision Viterbi decoder used for forward error-correction in a digital communication system have been investigated and compared. Each reinforcement learning neural network is designed to work as a co-processor to a demodulator dynamically adapting the soft quantization thresholds toward optimal settings in varying noise environments. The soft quantization thresholds of the demodulator are dynamically adjusted according to the previous performance of the Viterbi decoder, with updates occurring in fixed intervals (every 200 decoded bits out of the Viterbi decoder.) To facilitate implementaiton in digital hardware, each weight of the neural network and related parameters are specified as binary numbers. Computer simulation results demonstrate that, on average, the performance of a Viterbi decoder on an AWGN channel with nonuniformly-spaced soft decision thresholds dynamically adjusted by these neural networks is better than the performance of a Viterbi decoder with uniformly-spaced thresholds. This approach may be used for a variety of other digital communication applications such as channel estimation, adaptive equalization, and signal acquisition.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF01581961
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    Paper (German National Licenses)
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  • 4
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    A radial basis function neurocomputer implemented with analog VLSI circuits (1992)
    In:  Other Sources
    Details
    Publication Date: 2019-08-28
    Description: An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network architectures include reduced learning time and the ease of VLSI implementation. This neurocomputer is based on an analog/digital hybrid design and has been constructed with both custom analog VLSI circuits and a commercially available digital signal processor. The hybrid architecture is selected because it offers high computational performance while compensating for analog inaccuracies, and it features the ability to model large problems.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: In: IJCNN - International Joint Conference on Neural Networks, Baltimore, MD, June 7-11, 1992, Proceedings. Vol. 2 (A93-37001 14-63); p. II-607 to II-612.
    Format: text
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