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  • Design automation  (1)
  • Formate dehydrogenase  (1)
  • Key words. VLSI layout, Compaction, Graph constraints, Constraint graphs, Constraint reduction, Transitive reduction, Difference constraints.  (1)
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Keywords
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  • 1
    Electronic Resource
    Electronic Resource
    Formate dehydrogenase from Clostridium pasteurianum - Electron paramagnetic resonance spectroscopy of the redox active centers
    Amsterdam : Elsevier
    FEBS Letters 189 (1985), S. 263-266 
    Details
    ISSN: 0014-5793
    Keywords: Formate dehydrogenase ; Iron-sulfur protein ; Moco ; Pterin
    Source: Elsevier Journal Backfiles on ScienceDirect 1907 - 2002
    Topics: Biology , Chemistry and Pharmacology , Physics
    Type of Medium: Electronic Resource
    URL: http://linkinghub.elsevier.com/retrieve/pii/0014-5793(85)81036-X
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  • 2
    Electronic Resource
    Electronic Resource
    Area minimization for hierarchical floorplans (1996)
    Springer
    Algorithmica 15 (1996), S. 550-571 
    Details
    ISSN: 1432-0541
    Keywords: Design automation ; VLSI layout ; Floorplanning ; Floorplan sizing ; Area minimization ; NP-complete ; Hierarchical floorplans ; Pseudopolynomial
    Source: Springer Online Journal Archives 1860-2000
    Topics: Computer Science , Mathematics
    Notes: Abstract In this paper we study the area-minimization problem for hierarchical floorplans. We settle an open problem on the complexity of the area-minimization problem for hierarchical floorplans by showing it to be NP-complete (even for balanced hierarchical floorplans). We then present a new algorithm for determining the nonredundant realizations of a wheel. The algorithm has time costO(k 2 logk) and space cost0(k 2) if each block in a wheel has at mostk realizations. Based on the new algorithm for a wheel, we design a new pseudopolynomial area-minimization algorithm for hierarchical floorplans of order-5. The time and space costs of the algorithm are0((nM)2log(nM) and0(n 2 M), respectively, wheren is the number of basic blocks andM is an upper bound on the dimensions of the realizations of the basic blocks. The area-minimization algorithm was implemented. Experimental results show that it is very fast.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF01940881
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  • 3
    Electronic Resource
    Electronic Resource
    Optimal Graph Constraint Reduction for Symbolic Layout Compaction (1997)
    Springer
    Algorithmica 18 (1997), S. 560-574 
    Details
    ISSN: 1432-0541
    Keywords: Key words. VLSI layout, Compaction, Graph constraints, Constraint graphs, Constraint reduction, Transitive reduction, Difference constraints.
    Source: Springer Online Journal Archives 1860-2000
    Topics: Computer Science , Mathematics
    Notes: Abstract. The compaction problem in VLSI layout can be formulated as a linear program. To reduce the execution time and memory usage in compaction, it is important to reduce the size of the linear program. Since most constraints in compaction are derived directly or indirectly from physical separation and electrical connectivity requirements which can be expressed in the form of graph constraints, we study the graph constraint reduction problem. That is the problem of producing, for a given system of graph constraints, an equivalent system with the fewest graph constraints. After observing that the problem as previously formulated is NP-hard and overrestrictive in that the maximum possible reduction is not always attainable, we propose a new formulation in which the maximum possible reduction is guaranteed. We further present a polynomial-time algorithm for the new formulation.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/PL00009173
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