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  • 1
    Signatur: MOP Per 409/C(228)
    In: Technical memorandum
    Materialart: Monographie ausleihbar
    Seiten: 22 S. : Ill., graph. Darst.
    Serie: Technical memorandum / European Centre for Medium Range Weather Forecasts 228
    Sprache: Englisch
    Standort: MOP - Bitte bestellen
    Zweigbibliothek: GFZ Bibliothek
    Standort Signatur Erwartet Verfügbarkeit
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  • 2
    Digitale Medien
    Digitale Medien
    Springer
    Formal methods in system design 11 (1997), S. 5-21 
    ISSN: 1572-8102
    Schlagwort(e): Decision Diagrams (DDs) ; OKFDDs ; OBDDs ; OFDDs ; decomposition types ; exponential gaps
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Informatik
    Notizen: Abstract Ordered Decision Diagrams (ODDs) as a means for the representation of Boolean functions are used in many applications in CAD. Depending on the decomposition type, various classes of ODDs have been defined, among them being the Ordered Binary Decision Diagrams (OBDDs), the Ordered Functional Decision Diagrams (OFDDs) and the Ordered Kronecker Functional Decision Diagrams (OKFDDs). Based on a formalization of the concept decomposition type we first investigate all possible decomposition types and prove that already OKFDDs, which result from the application of only three decomposition types, result in the most general class of ODDs. We then show from a (more) theoretical point of view that the generality of OKFDDs is really needed. We prove several exponential gaps between specific classes of ODDs, e.g. between OKFDDs on the one side and OBDDs, OFDDs on the other side. Combining these results it follows that a restriction of the OKFDD concept to subclasses, such as OBDDs and OFDDs as well, results in families of functions which lose their efficient representation.
    Materialart: Digitale Medien
    Standort Signatur Erwartet Verfügbarkeit
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  • 3
    Digitale Medien
    Digitale Medien
    Springer
    Journal of electronic testing 7 (1995), S. 173-191 
    ISSN: 1573-0727
    Schlagwort(e): design for testability ; path delay fault model ; testability preserving transformations ; testability inproving transformations
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract Several synthesis for path delay fault (PDF) testability approaches are based on local transformations of digital circuits. Different methods were used to show that transformations preserve or improve PDF testability. In this paper we present a new unifying approach to show that local transformations preserve or improve PDF testability. This approach can be applied to every local transformation and in contrast to previously published methods only the subcircuits to be transformed have to be considered. Using our new approach we are able to show in a very convenient way that the transformations which are already used in synthesis tools preserve or improve PDF testability. We present further transformations which preserve or improve testability. We show that a transformation, claimed to preserve PDF testability, in fact, does not do so. Moreover, the testability improving factor which is a unit of measurement for the quality of testability improving transformations is introduced. Additionally, we present the capabilities of SALT (system forapplication oflocaltransformations), which is a general tool for application of a predefined set of local transformations. The implementation of SALT is described and it is shown how the isomorphism of a “pattern to be searched” and a “matched subcircuit” can be weakened to allow the application of local transformations more frequently. Finally, we confirm the theoretical part of this paper by experimental results obtained by application of the examined local transformations to several benchmark circuits. The effect of these transformations (and combinations of different types of transformations) on PDF testability, size and depth of the transformed circuits is examined and encouraging results are presented. For example, a reduction of up to 90% can be observed for the number of untestable paths.
    Materialart: Digitale Medien
    Standort Signatur Erwartet Verfügbarkeit
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  • 4
    Digitale Medien
    Digitale Medien
    Springer
    Journal of electronic testing 15 (1999), S. 219-238 
    ISSN: 1573-0727
    Schlagwort(e): fault simulation ; symbolic simulation ; SOT ; MOT ; BDD
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract We present a fault simulator for synchronous sequential circuits that combines the efficiency of three-valued logic simulation with the exactness of a symbolic approach. The simulator is hybrid in the sense that three different modes of operation—three-valued, symbolic and mixed—are supported. We demonstrate how an automatic switching between the modes depending on the computational resources and the properties of the circuit under test can be realized, thus trading off time/space for accuracy of the computation. Furthermore, besides the usual Single Observation Time Test Strategy (SOT) for the evaluation of the fault coverage, the simulator supports evaluation according to the more general Multiple Observation Time Test Strategy (MOT). Numerous experiments are given to demonstrate the feasibility and efficiency of our approach. In particular, it is shown that, at the expense of a reasonable time penalty, the exactness of the fault coverage computation can be improved even for the largest benchmark functions.
    Materialart: Digitale Medien
    Standort Signatur Erwartet Verfügbarkeit
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  • 5
    Digitale Medien
    Digitale Medien
    Springer
    Journal of electronic testing 14 (1999), S. 219-225 
    ISSN: 1573-0727
    Schlagwort(e): AND/EXOR ; 2-level circuits ; random pattern testability ; synthesis for testability
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract It is often stated that AND/EXOR circuits are much easier to test than AND/OR circuits. This statement, however, only holds true for circuits derived from restricted classes of AND/EXOR expressions, like positive polarity Reed-Muller and fixed polarity Reed-Muller expressions. For these two classes of expressions, circuits with good deterministic testability properties are known. In this paper we show that these circuits also have good random pattern testability attributes. An input probability distribution is given that yields a short expected test length for biased random patterns. This is the first time theoretical results on random pattern testability are presented for 2-level AND/EXOR circuit realizations of arbitrary Boolean functions. It turns out that analogous results cannot be expected for less restricted classes of 2-level AND/EXOR circuits. We present experiments demonstrating that generally minimized 2-level AND/OR circuits can be tested as easy (or hard) as minimized 2-level AND/EXOR circuits.
    Materialart: Digitale Medien
    Standort Signatur Erwartet Verfügbarkeit
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  • 6
    Publikationsdatum: 1997-05-01
    Print ISSN: 0022-2836
    Digitale ISSN: 1089-8638
    Thema: Biologie
    Publiziert von Elsevier
    Standort Signatur Erwartet Verfügbarkeit
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  • 7
    Publikationsdatum: 1996-10-01
    Print ISSN: 0003-0007
    Digitale ISSN: 1520-0477
    Thema: Geographie , Physik
    Standort Signatur Erwartet Verfügbarkeit
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