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  • 1
    Electronic Resource
    Electronic Resource
    Hybrid Fault Simulation for Synchronous Sequential Circuits (1999)
    Springer
    Journal of electronic testing 15 (1999), S. 219-238 
    Details
    ISSN: 1573-0727
    Keywords: fault simulation ; symbolic simulation ; SOT ; MOT ; BDD
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract We present a fault simulator for synchronous sequential circuits that combines the efficiency of three-valued logic simulation with the exactness of a symbolic approach. The simulator is hybrid in the sense that three different modes of operation—three-valued, symbolic and mixed—are supported. We demonstrate how an automatic switching between the modes depending on the computational resources and the properties of the circuit under test can be realized, thus trading off time/space for accuracy of the computation. Furthermore, besides the usual Single Observation Time Test Strategy (SOT) for the evaluation of the fault coverage, the simulator supports evaluation according to the more general Multiple Observation Time Test Strategy (MOT). Numerous experiments are given to demonstrate the feasibility and efficiency of our approach. In particular, it is shown that, at the expense of a reasonable time penalty, the exactness of the fault coverage computation can be improved even for the largest benchmark functions.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008376522451
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  • 2
    Electronic Resource
    Electronic Resource
    Testability of 2-Level AND/EXOR Circuits (1999)
    Springer
    Journal of electronic testing 14 (1999), S. 219-225 
    Details
    ISSN: 1573-0727
    Keywords: AND/EXOR ; 2-level circuits ; random pattern testability ; synthesis for testability
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract It is often stated that AND/EXOR circuits are much easier to test than AND/OR circuits. This statement, however, only holds true for circuits derived from restricted classes of AND/EXOR expressions, like positive polarity Reed-Muller and fixed polarity Reed-Muller expressions. For these two classes of expressions, circuits with good deterministic testability properties are known. In this paper we show that these circuits also have good random pattern testability attributes. An input probability distribution is given that yields a short expected test length for biased random patterns. This is the first time theoretical results on random pattern testability are presented for 2-level AND/EXOR circuit realizations of arbitrary Boolean functions. It turns out that analogous results cannot be expected for less restricted classes of 2-level AND/EXOR circuits. We present experiments demonstrating that generally minimized 2-level AND/OR circuits can be tested as easy (or hard) as minimized 2-level AND/EXOR circuits.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008306002882
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    Paper (German National Licenses)
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