ALBERT

All Library Books, journals and Electronic Records Telegrafenberg

feed icon rss

Ihre E-Mail wurde erfolgreich gesendet. Bitte prüfen Sie Ihren Maileingang.

Leider ist ein Fehler beim E-Mail-Versand aufgetreten. Bitte versuchen Sie es erneut.

Vorgang fortführen?

Exportieren
  • 1
    Digitale Medien
    Digitale Medien
    Springer
    Analog integrated circuits and signal processing 15 (1998), S. 277-290 
    ISSN: 1573-1979
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract One-dimensional cellular array processor architecture and design for neural-based partial response (PR) signal detection are presented. Analog parallel computing approaches have many attractive advantages in achieving low power, low cost, and faster processing speed by its uniquely coupled parallel and distributed processing nature. In this paper, we describe the maximum likelihood sequence estimation (MLSE) algorithm for PR signals, the enhanced Cellular Neural Network (CNN) processor array architecture to realize the detection algorithm, and system performance evaluation. Analytical models and simulations on a design example of the detector have been employed to demonstrate the advantages of this scalable VLSI architecture. A processing rate of 265 Mbps was achieved for a prototype detector on a silicon area of 5.14 mm by 5.81 mm is a 1.2 µm CMOS technology. The processing rate can be beyond 1Gbps if it is implemented in the same amount of silicon area by using 0.5 µm CMOS technology. Such promising results clearly demonstrate the ability to meet the needs in future high speed data communication by VLSI realization of maximum likelihood sequence detectors based on the enhanced cellular neural network paradigm.
    Materialart: Digitale Medien
    Standort Signatur Erwartet Verfügbarkeit
    BibTip Andere fanden auch interessant ...
  • 2
    Digitale Medien
    Digitale Medien
    Springer
    Analog integrated circuits and signal processing 1 (1991), S. 75-87 
    ISSN: 1573-1979
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract A systematic method for automatic layout synthesis of analog integrated circuit modules is presented. This method uses analog circuit recognition and critical net analysis techniques to derive proper layout constraints for analog circuit performance optimization. These layout constraints are analyzed and prioritized according to the recognized analog circuit topologies and classified net sensitivities. The weighted constraints are then used to drive the physical layout generation process to obtain a high-quality custom circuit layout. An efficient, constraint-driven analog floorplanning technique based on a zone-sensitivity partitioning algorithm is specially developed to generate a slicing floorplan incorporating the layout constraints. This layout synthesis approach has three key advantages. First, it can produce a satisfactory analog circuit performance with negligible degradation due to the layout-introduced parasitic effects. Second, it allows a complete automation for netlist-to-layout synthesis so that the layout tool can be used by VLSI system designers. Finally, this method is quite general and can be applied to handle a wide variety of analog circuits. Experimental results in CMOS operational amplifiers and a comparator are presented.
    Materialart: Digitale Medien
    Standort Signatur Erwartet Verfügbarkeit
    BibTip Andere fanden auch interessant ...
  • 3
    Digitale Medien
    Digitale Medien
    Springer
    Analog integrated circuits and signal processing 2 (1992), S. 105-115 
    ISSN: 1573-1979
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract The pseudoboundary method is an engineering technique to extend the use of a single parameter set over the entire geometric design space for VLSI circuits. The technique eliminates adverse effects, such as negative output conductance, by clamping the evaluation of geometric dependence terms at the systematically determined boundaries of a primary region. The use of this technique is essential for accurate simulation of analog and digital circuits as well as prediction of circuit performance using next-generation submicron VLSI fabrication technologies. Results demonstrating the effectiveness of the technique using the widely accepted Berkeley short-channel IGFET model (BSIM) are presented, with data from transistors of different geometries ranging from 0.5 to 70 μm.
    Materialart: Digitale Medien
    Standort Signatur Erwartet Verfügbarkeit
    BibTip Andere fanden auch interessant ...
  • 4
    Digitale Medien
    Digitale Medien
    Springer
    Analog integrated circuits and signal processing 5 (1994), S. 121-133 
    ISSN: 1573-1979
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract Effective parameter extraction is a crucial step in accurate simulation of microelectronic circuits and systems. A parameter extraction program, which is based on a global optimization algorithm, uses a single objective function that minimizes the drain current error between the predicted and measured data. Parameter sets extracted on this basis are adequate for the purpose of digital circuit simulation, but fall short of simulation requirements for analog circuits. The use of a multiple-objective function is proposed, which simultaneously optimizes several critical electrical quantities including the drain current, output conductance, and transconductance. Experimental results with the multiple-objective function are presented, to show the improvement in extracted parameters. The recently developed BSIM_plus MOS transistor model for sub-half-micron integrated circuits uses a compact set of parameters, which greatly enhances the ability to accurately extract parameter values. This model was implemented into the parameter extraction program and some extraction results are presented. The parameter space has several local minima within which a gradient descent method may be trapped. Simulated annealing techniques can be applied to find near-optimal solutions of problems containing multiple local minima in their solution spaces. Experimental results showing the optimization of drain current error using simulation annealing techniques are presented.
    Materialart: Digitale Medien
    Standort Signatur Erwartet Verfügbarkeit
    BibTip Andere fanden auch interessant ...
  • 5
    Digitale Medien
    Digitale Medien
    Springer
    Analog integrated circuits and signal processing 6 (1994), S. 105-119 
    ISSN: 1573-1979
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract A fourth-order interpolative modulator was designed and fabricated in a 2-µm CMOS technology. As a key building block, a fully-differential folded-cascode operational amplifier has been developed and successfully tested. The main design emphasis is placed on achieving a fast settling behavior. The fully-differential analog modulator operates at the rate of 5.12MHz and provides a signal-to-noise ratio higher than 96dB for 16-bit analog-to-digital conversion.
    Materialart: Digitale Medien
    Standort Signatur Erwartet Verfügbarkeit
    BibTip Andere fanden auch interessant ...
  • 6
    Digitale Medien
    Digitale Medien
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 5 (1993), S. 185-199 
    ISSN: 1573-109X
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract An analog computing-based systolic architecture which employs multiple neuroprocessors for high-speed early vision processing is presented. For a two-dimensional image, parallel processing is performed in the row direction and pipelined processing is performed in the column direction. The mixed analog/digital design approach is suitable for implementation of electronic neural systems. Local data computation is executed by analog circuitry to achieve full parallelism and to minimize power dissipation. Inter-processor communication is carried out in the digital format to maintain strong signal strength across the chip boundary and to achieve direct scalability in neural network size. For demonstration purposes, a compact and efficient VLSI neural chip that includes multiple neuroprocessors for high-speed digital image restoration is designed. Measured results of the programmable synapse, and statistical distribution of measured synapse conductances are presented. Based on these results, system-level analyses at 8-bit resolution are conducted. A 8.0×6.0-mm 2 chip from a 1.2-µm CMOS technology can accommodate 5 neuroprocessors and the speed-up factor over the Sun-4/75 SPARC workstation is around 450. This chip achieves 18 Giga connections per second.
    Materialart: Digitale Medien
    Standort Signatur Erwartet Verfügbarkeit
    BibTip Andere fanden auch interessant ...
  • 7
    Digitale Medien
    Digitale Medien
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 6 (1993), S. 57-66 
    ISSN: 1573-109X
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract VLSI design of a competitive neural network for video motion detection is presented. Massively parallel neurocomputing is performed by compact and efficient neuroprocessors. Local data transfer between the neuroprocessors is carried out by using an analog point-to-point interconnection scheme, while global data communication between the host computer and neuroprocessors is achieved through a digital common bus. Experimental results of the analog circuit blocks and system-level analysis on a sequence of real-world images are also presented.
    Materialart: Digitale Medien
    Standort Signatur Erwartet Verfügbarkeit
    BibTip Andere fanden auch interessant ...
  • 8
    Digitale Medien
    Digitale Medien
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 8 (1994), S. 267-282 
    ISSN: 1573-109X
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract Artificial neural network chips can achieve high-speed performance in solving complex computational problems for signal and information processing applications. These chips contain regular circuit units such as synapse matrices that interconnect linear arrays of input and output neurons. The neurons and synapses may be implemented in an analog or digital design style. Although the neural processing has some degree of fault tolerance, a significant percentage of processing defects can result in catastrophic failure of the neural network processors. Systematic testing of these arrays of circuitry is of great importance in order to assure the quality and reliability of VLSI neural network processor chips. The proposed testing method consists of parametric test and behavioral test. Two programmable analog neural chips have been designed and fabricated. The systematic approach used to test the chips is described, and measurement results on parametric test are presented.
    Materialart: Digitale Medien
    Standort Signatur Erwartet Verfügbarkeit
    BibTip Andere fanden auch interessant ...
  • 9
    Digitale Medien
    Digitale Medien
    Springer
    Analog integrated circuits and signal processing 15 (1998), S. 201-213 
    ISSN: 1573-1979
    Schlagwort(e): Mixed-Signal ; VLSI ; Neural Networks ; Hippocampus ; Parallel Processing
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract The hippocampal region of the brain system can be analyzed with the nonlinear system modeling approach. The input-output relationship of the neural units is best represented by the kernel functions of different complexities. The modeling expression of the first and second order kernels are computed in analog current-mode instead of digital data processing in order to fully explore massively parallel processing capability of the neural networks. Two distinct methods are utilized: the table-look-up approach and the model-based approach. The former can achieve high accuracy but consumes large silicon area while the latter saves silicon area and maintains moderately high accuracy. Circuit-level simulation results and experimental data from two test structures are presented.
    Materialart: Digitale Medien
    Standort Signatur Erwartet Verfügbarkeit
    BibTip Andere fanden auch interessant ...
  • 10
    Digitale Medien
    Digitale Medien
    Springer
    Analog integrated circuits and signal processing 2 (1992), S. 19-25 
    ISSN: 1573-1979
    Quelle: Springer Online Journal Archives 1860-2000
    Thema: Elektrotechnik, Elektronik, Nachrichtentechnik
    Notizen: Abstract Simple floating-gate transistors fabricated by a conventional double-polysilicon process show excellent programming and charge-retention characteristics. A five-transistor synapse cell achieves 8-bit resolution and at least 6-bit accuracy for analog neural computation. It occupies 67 μm×73 μm in a 2-μm CMOS process and can retain charge accuracy for over 25 years.
    Materialart: Digitale Medien
    Standort Signatur Erwartet Verfügbarkeit
    BibTip Andere fanden auch interessant ...
Schließen ⊗
Diese Webseite nutzt Cookies und das Analyse-Tool Matomo. Weitere Informationen finden Sie hier...