Publication Date:
1996-01-01
Description:
This paper describes the design of an ASIC chip for thinning of graylevel images. The chip implements a Min-Max skeletonization algorithm and is based on a pipeline architecture where each stage of the pipeline performs masking operations on the graylevel images. The chip operates in real time at a frequency of 8 MHz and utilizes about 321 mils × 410 mils of silicon area.
Print ISSN:
1065-514X
Electronic ISSN:
1563-5171
Topics:
Electrical Engineering, Measurement and Control Technology