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Adaptive Voltage Scaling with In-Situ Detectors in Commercial FPGAs (2014)

Institute of Electrical and Electronics Engineers (IEEE)

In: IEEE Transactions on Computers (T-C)

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Publication Date: 2014-12-13

Description: This paper investigates the limits of adaptive voltage scaling (AVS) applied to commercial FPGAs which do not specifically support voltage adaptation. An adaptive power architecture based on a modified design flow is created with in-situ detectors and dynamic reconfiguration of clock management resources. AVS is a power-saving technique that enables a device to regulate its own voltage and frequency based on workload, process and operating conditions in a closed-loop configuration. It results in significant improved energy profiles compared with dynamic voltage frequency scaling (DVFS) in which the device uses a number of pre-calculated valid working points. The results of deploying AVS in FPGAs with in-situ detectors shows power and energy savings exceeding 85 percent compared with nominal voltage operation at the same frequency. The in-situ detector approach compares favorably with critical path replication based on delay lines since it avoids the need of cumbersome and error-prone delay line calibration.

Print ISSN: 0018-9340

Electronic ISSN: 1557-9956

Topics: Computer Science

Published by Institute of Electrical and Electronics Engineers (IEEE) on behalf of The IEEE Computer Society.

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