Publikationsdatum:
2019-06-28
Beschreibung:
Design, modeling, analysis, and simulation of a phase-locked loop (PLL) with a digital loop filter are presented in this article. A TMS320C25 digital signal processor (DSP) is used to implement this digital loop filter. In order to keep the compatibility, the main design goal was to replace the analog PLL (APLL) of the Deep-Space Transponder (DST) receiver breadboard's loop filter with a digital loop filter without changing anything else. This replacement results in a hybrid digital PLL (HDPLL). Both the original APLL and the designed HDPLL are Type I second-order systems. The real-time performance of the HDPLL and the receiver is provided and evaluated.
Schlagwort(e):
ELECTRONICS AND ELECTRICAL ENGINEERING
Materialart:
The Telecommunications and Data Acquisition Report; p 175-189
Format:
application/pdf
