ISSN:
1089-7550
Source:
AIP Digital Archive
Topics:
Physics
Notes:
In this study, we report a high-performance ultrathin oxide (≈80 A(ring)) prepared by a low-temperature wafer loading and N2 preannealing before oxidation. This recipe can reduce native oxide thickness and thermal stress compared to the conventional oxidation recipe. The high-resolution transmission electron microscopy reveals that the SiO2/Si interface is atomically flat, and a thin crystalline-like oxide layer about 7 A(ring) exists at the interface. Oxides prepared by the proposed recipe show a very high dielectric breakdown field (≥16 MV/cm) and a very low interface state density (Nit ≈ 3 × 109 eV−1 cm−2 at midgap). The effective barrier height at cathode derived from the slopes of log(Jg/E2ox) vs 1/Eox and tbd vs 1/Eox plots is about 3.9 eV, instead of 3.2 eV for the control sample. It also shows a better immunity to the charge trapping and interface state generation under high-field stressing, and superior time-dependent dielectric breakdown characteristics.
Type of Medium:
Electronic Resource
URL:
http://dx.doi.org/10.1063/1.351749
