ALBERT

All Library Books, journals and Electronic Records Telegrafenberg

X
feed icon rss

Your email was sent successfully. Check your inbox.

An error occurred while sending the email. Please try again.

Proceed reservation?

Export
Filter
  • Articles  (20)
  • resistivity  (10)
  • test generation  (10)
  • Springer  (20)
  • 1990-1994  (17)
  • 1985-1989  (3)
  • 1960-1964
  • 1950-1954
  • Electrical Engineering, Measurement and Control Technology  (20)
Collection
  • Articles  (20)
Source
Keywords
Publisher
  • Springer  (20)
Years
Year
Topic
  • 1
    Electronic Resource
    Electronic Resource
    Design of a C-testable booth multiplier using a realistic fault model (1994)
    Springer
    Journal of electronic testing 5 (1994), S. 29-41 
    Details
    ISSN: 1573-0727
    Keywords: Array multipliers ; C-testability ; design for testability ; fault modelling ; test generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A Booth multiplier is the most widely used type of multiplier. In this article, the testability issues involved in its design are discussed. In contrast to previous work, the fault model includes not only node stuck-at faults, but also transistor stuck-open and stuck-close faults. Moreover, as a result of adopting a hierarchical testability approach, the designed Booth multiplier turns out to be fully C-testable. To achieve this C-testability, only three additional controllable inputs are required, which results in a negligible area and delay overhead.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00971961
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 2
    Electronic Resource
    Electronic Resource
    Electron tunneling into high-T c cuprates: The case of Y1−x Pr x Ba2Cu3O7−δ (1994)
    Springer
    Journal of superconductivity 7 (1994), S. 345-348 
    Details
    ISSN: 1572-9605
    Keywords: Tunneling ; Y1−xPrxBa2Cu3O7−δ ; resistivity ; energy gap
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology , Physics
    Notes: Abstract Many different forms of superconducting tunneling have been attempted with the high-T c cuprates. For these studies to be convincing, it is important to assure that elastic tunneling is the dominant conduction mechanism in the structures considered. Some simple criteria to determine whether this is the case are reviewed, and then our results (which satisfy the criteria) on the system Y1−xPrxBa2Cu3O7−δ are discussed. In this study we show that with increasing Pr concentration, the material becomes more gapless.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00724566
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 3
    Electronic Resource
    Electronic Resource
    Temperature dependence of the infrared optical properties of YBa2Cu3O7: A plasmon damping model (1994)
    Springer
    Journal of superconductivity 7 (1994), S. 481-483 
    Details
    ISSN: 1572-9605
    Keywords: High-T c superconductors ; YBa2Cu3O7 ; infrared ; plasmon ; resistivity
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology , Physics
    Notes: Abstract The temperature dependence observed in the mid- and near-infrared optical properties of YBa2Cu3O7 is explained in terms of the Drude model for free charge carriers. In the Drude model, the linear temperature dependence of the dc resistivity arises from the free charge carriers having a temperature-dependent mean free path. This temperature dependence results in the plasmon contribution to the dielectric constant having a damping coefficient which also varies linearly with temperature. We find that the temperature dependence which is observed in the absorption and reflection spectra of YBa2Cu3O7 is consistent with this simple model.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00724594
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 4
    Electronic Resource
    Electronic Resource
    Anisotropic uniaxial pressure effects in YBa2Cu3O7−δ (1994)
    Springer
    Journal of superconductivity 7 (1994), S. 159-164 
    Details
    ISSN: 1572-9605
    Keywords: Uniaxial pressure dependence ; YBa2Cu3O7−δ ; resistivity
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology , Physics
    Notes: Abstract We present measurements of the uniaxial pressure dependence ofT c of untwinned YBa2Cu3O7−δ crystals with various oxygen stoichiometries. For all samples investigated,T c decreases for pressure alonga, increases for pressure alongb, and, in oxygen deficient samples, increases strongly for pressure alongc. These results are compared to the behavior found in the La2−x Sr x CuO4 and YBa2Cu4O8 systems. Neither the model of pressure-induced charge transfer nor coupling to orthorhombic distortions can explain all the data. However, the presence of singularities in the electronic density of states close to the Fermi energy is a possible origin of the observed behavior. Our preliminary data on the pressure dependence of thec-axis and in-plane resistivities in twinned crystals are consistent with this view.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00730387
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 5
    Electronic Resource
    Electronic Resource
    Electronic specific heat of Tl2Ba2CuO6+δ from 2 K to 300 K for 0≤δ≤0.1 (1994)
    Springer
    Journal of superconductivity 7 (1994), S. 261-264 
    Details
    ISSN: 1572-9605
    Keywords: Overdoped Tl2Ba2CuO6+δ ; electronic heat capacity ; resistivity ; pair breaking
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology , Physics
    Notes: Abstract Using a high-precision differential technique with a resolution of 1∶104, we have measured the heat capacity of Tl2Ba2CuO6+δ over a temperature range 2–300 K for 0≤δ≤0.1. Anomalies atT c are seen for all superconducting compositions measured, and the results are consistent with a temperature- andδ-independent normal-state electronic termγ n∼0.6 mJ/g-at. K2. The samples with the largerT c 's exhibit strong fluctuations in their specific heat, typical of a highly anisotropic 2D superconductor, but there is some evidence that these fluctuations become weaker atT c falls-consistent with an increase in the coherence length on hole doping. At temperatures below 5 K an upturn in the data is observed which appears to increase in magnitude asT c falls, correlating with the increase in the Curie term of published susceptibility data.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00730408
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 6
    Electronic Resource
    Electronic Resource
    Lattice and spin bipolarons in metal oxides and doped fullerenes (1994)
    Springer
    Journal of superconductivity 7 (1994), S. 599-605 
    Details
    ISSN: 1572-9605
    Keywords: Bipolarous ; spin ; NMR ; Hall effect ; resistivity
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology , Physics
    Notes: Abstract We extrapolate the BCS theory to the strong electron-phonon and (or) electron-spin fluctuation interaction and show that in the strong-coupling limit the ground state is a charged Bose liquid of lattice and (or) spin bipolarons. Kinetic and thermodynamic properties of charged bosons on a lattice in the normal and superconducting states are discussed, and some evidence for the model is given from NMR, neutron scattering, near-infrared absorption, Hall effect, resistivity, thermal conductivity, isotope effect, heat capacity, and critical magnetic fields of high-T c oxides. The maximum attainableT c is estimated to be in the region of the transition from the Fermi liquid to a charged Bose liquid (polaronic superconductivity). The proposed theory is not restricted by low dimensionality and might be applied to cubic oxides such as the “old” BaPbBiO and to alkali-doped C60 as well.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00728467
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 7
    Electronic Resource
    Electronic Resource
    Synchronizing sequences and symbolic traversal techniques in test generation (1993)
    Springer
    Journal of electronic testing 4 (1993), S. 19-31 
    Details
    ISSN: 1573-0727
    Keywords: Binary decision diagram ; implicit state enumeration ; multiple observation time ; synchronizing sequence ; test generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Asynchronizing sequence drives a circuit from an arbitrary power-up state into a unique state. Test generation on a circuit without a reset state can be much simplified if the circuit has a synchronizing sequence. In this article, a framework and algorithms for test generation based on themultiple observation time strategy are developed by taking advantage of synchronizing sequences. Though it has been shown that the multiple observation time strategy can provide a higher fault coverage than the conventional single observation time strategy, until now the multiple observation time strategy has required a very complex tester operation model (referred asMultiple Observation time-Multiple Reference strategy (MOMR) in the sequel) over the conventional tester operation model. The overhead of MOMR, exponential in the worst case, has prevented widespread use of the method. However, when a circuit is synchronizable, test generation can employ the multiple observation time strategy and provide better fault coverages, without resorting to MOMR. This testing strategy is referred asMultiple Observation time-Single Reference strategy (MOSR). We prove in this article that the same fault coverage, that could be achieved in MOMR, can be obtained in MOSR, if the circuit under test generation is synchronizable. We investigate how a synchronizing sequences simplifies test generation and allows to use MOSR under multiple observation time strategy. The experimental results show that higher fault coverages and large savings in CPU time can be achieved by the proposed framework and algorithms over both existing single observation time strategy methods as well as other multiple observation time strategy methods.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00971937
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 8
    Electronic Resource
    Electronic Resource
    A synthesis-based test generation and compaction algorithm for multifaults (1993)
    Springer
    Journal of electronic testing 4 (1993), S. 91-104 
    Details
    ISSN: 1573-0727
    Keywords: Iogic synthesis ; multiple fault ; test compaction ; test generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Because of its inherent complexity, the problem of automatic test pattern generation for multiple stuck-at faults (multifaults) has been largely ignored. Recently, the observation that multifault testability is retained by algebraic factorization demonstrated that single fault (and therefore multifault) vector sets for two-level circuits could give complete multifault coverage for multilevel circuits constructed by algebraic factorization. Unfortunately, in using this method the vector set size can be much larger than what is really required to achieve multifault coverage, and the approach has some limitations in its applicability. In this article we first present a multifault test generation and compaction strategy for algebraically factored multilevel circuits, synthesized from two-level representations. We give a basic sufficiency condition for multifault testability of such networks. We next focus on the relationship between hazard-free robust path-delay-fault testability and multifault testability. We show that the former implies the latter for arbitrary multilevel circuits. This allows the use of previously developed composition rules that maintain path-delay-fault testability for the synthesis of multifault testable circuits. We identify a class of multiplexor-based networks and prove an interesting property of such networks—if the networks are fully single stuck-at fault testable, or made fully single stuck-at fault testable, they are completely multifault testable. We give a multifault test generation and compaction algorithm for such networks. We provide experimental results which indicate that a compacted multifault test set derived using the above strategies can be significantly smaller than the test set derived using previously proposed procedures. These results also indicate the substantially wider applicability of our procedures, as compared to previous techniques.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00971942
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 9
    Electronic Resource
    Electronic Resource
    The optimistic update theorem for path delay testing in sequential circuits (1993)
    Springer
    Journal of electronic testing 4 (1993), S. 285-290 
    Details
    ISSN: 1573-0727
    Keywords: Fault simulation ; path delay faults ; test generation ; timing analysis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract For sequential circuit path delay testing, we propose a new update rule for state variables whereby flipflops are updated with their correct values provided they are destinations of at least one robustly activated path delay fault. Existing algorithms in the literature, for robust fault simulation and test generation, assign unknown values to off-path latches that have non-steady signals at their inputs in the previous vector. Such procedures are pessimistic and predict low fault coverages. They also have an adverse effect on the execution time of fault simulation especially if the circuit has a large number of active paths. The proposed update rule avoids these problems and yet guarantees robustness.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00971977
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 10
    Electronic Resource
    Electronic Resource
    Resistivity and magnetic susceptibility studies of TlmCan−1Ba2CunOy before and after doping with LiF (1993)
    Springer
    Journal of superconductivity 6 (1993), S. 111-118 
    Details
    ISSN: 1572-9605
    Keywords: LiF-doped TlCaBaCuO ; resistivity ; susceptibility
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology , Physics
    Notes: Abstract Measurements of the superconducting resistance as a function of temperature were performed using the conventional four-probe method. The transition to complete superconductivity was recorded for samples of (Tl2Ca2Ba2Cu3O10)100−xLiF x (2223) mixed with different LiF ratiosx=0, 2, 4, 5, 6, 8, 10, and 12 wt.%. It was found that the transition temperatureT c was increased up to 5 wt.% of LiF. Further addition of LiF decreasesT c . Therefore, 5 wt.% LiF is the optimum concentration giving a transition temperature of 130 K. Measurements of the superconducting resistance of all the samples except the (1111) compound show that the addition of 5 wt.% LiF increasesT c and decreases the metastable phases. The real part of the a.c. magnetic susceptibilityϰ a.c. is studied using a zero-field cooled mechanism. The temperature dependence ofϰ a.c. for the prepared TlBaCaCuO having stoichiometric composition of (1111), (2223), (2234), and (3245) and that after doping with 5 wt.% LiF showed a broad feature. The transition to the complete diamagnetic state takes place in a broad transition region containing many transition steps, indicating the presence of metastable phases. The addition of LiF decreases the fluctuation in the transition region and its effect in reducing the number of multiphases.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00617810
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 11
    Electronic Resource
    Electronic Resource
    A test methodology for finite state machines using partial scan design (1992)
    Springer
    Journal of electronic testing 3 (1992), S. 127-137 
    Details
    ISSN: 1573-0727
    Keywords: ATPG ; fault ; partial scan ; loop-free circuits ; test generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper presents an efficient automatic test pattern generation technique for loop-free circuits. A partial scan technique is used to convert a sequential circuit (finite state machine) with arbitrary feedback paths into a pipelined circuit for testing. Test generation for these modified circuits can be performed with a modified combinational automatic test pattern generator (ATPG), which is much faster than a sequential ATPG. A combinational model is obtained by replacing all flipflops by buffers. It is shown that a test vector for a fault in this model obtained by a combinational test generator can be expanded into a sequence of identical vectors to detect the same fault in the original sequential circuit. This technique may abort a few faults which can then be resolved with a sequential ATPG. Experiments on the ISCAS89 circuits show that only 30% to 70% of flipflops require scanning in larger circuits and 96% to 100% fault coverage for almost all the circuits without resorting to a sequential ATPG.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00137250
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 12
    Electronic Resource
    Electronic Resource
    Generation and evaluation of current and logic tests for switch-level sequential circuits (1992)
    Springer
    Journal of electronic testing 3 (1992), S. 359-366 
    Details
    ISSN: 1573-0727
    Keywords: Current tests ; I DDQ ; logic tests ; test generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This article presents an approach to developing high quality tests for switch-level circuits using both current and logic test generation algorithms. Faults that are aborted or undetectable by logic tests may be detected by current tests, or vice versa. An efficient switch level test generation algorithm for generating current and logic tests is introduced. Clear definitions for analyzing the effectiveness of the joint test generation approach are derived. Experimental results are presented for demonstrating high coverage of stuck-at, stuck-on, and stuck-open faults for switch level circuits when both current and logic tests are used.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00135339
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 13
    Electronic Resource
    Electronic Resource
    Phase-slip resistivity in high-temperature superconductors: a manifestation of intrinsic nano-granularity (1992)
    Springer
    Journal of superconductivity 5 (1992), S. 67-74 
    Details
    ISSN: 1572-9605
    Keywords: Flux flow ; phase slip ; Josephson junctions ; resistivity
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology , Physics
    Notes: Abstract Several critical experiments have shown that the so-called “background” magnetoresistance which occurs with no Lorentz force activation is isotropic in thea-b plane. This isotropic resistivity is linked to paradoxical behavior of vortices which cannot be changed by pinning, a result which may imply intrinsic pinning. Nevertheless, a number of flux-flow observations indicate that vortices may also behave as if they were unpinned. An explanation is proposed which states that this behavior arises as a consequence of defects in oxygen ordering in the Cu-O planes of HTSC crystals; this explanation involves segmentation of the Cu-O planes, and Josephson coupling between adjacent segments. The effective junction areas are seen to be very small, with dimensions characteristic of the size of the unit cell. Thermal motion of nano-scale weak links resolves the pinning paradox by inducing phase-slip resistive dissipation. The resulting phase-slip resistivity is shown to have axial symmetry, that is, the resistivity is independent of the angle between the current and the applied field, with both in thea-b plane.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00617998
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 14
    Electronic Resource
    Electronic Resource
    Fault modeling and fault equivalence in CMOS technology (1991)
    Springer
    Journal of electronic testing 2 (1991), S. 229-241 
    Details
    ISSN: 1573-0727
    Keywords: Fault modeling ; fault equivalence ; fault collapsing ; test generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract The need for greater reliability in the fault coverage of test sequences for VLSI circuits has led to the proposal for more accurate fault models and test pattern generation tools. Such improvements bring about a large increase in the fault list to be considered and in the CPU time needed to generate the test. In this article, we propose a global modeling allowing the definition of fault equivalence criteria in order to reduce the set of faults to be handled by the test pattern generation process for CMOS circuits. The proposed approach is based on a switch level description of the circuit. To perform fault equivalence on such descriptions, circuit modifications are introduced using subnetwork partitioning. The fault models taken into account are classical in CMOS technology, i.e., stuck-at, stuck-on, stuck-open, shorts and opens.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00135440
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 15
    Electronic Resource
    Electronic Resource
    Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling (1991)
    Springer
    Journal of electronic testing 2 (1991), S. 351-372 
    Details
    ISSN: 1573-0727
    Keywords: Built-in self-test ; design-for-testability ; iterative logic array ; pseudo-exhaustive test ; test generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract In this article we discuss a test generation, design-for-testability and built-in self-test methodology for two-dimensional iterative logic arrays (ILAs) that perform arithmetic functions. Our approach is unique because a single graph labeling procedure is used to generate test vectors, implement design-for-testability as well as design the circuitry for built-in self-test. The graph labeling is based on mathematical properties of full-addition such as symmetry and self-duality. Circuit modifications are introduced by a systematic procedure based on the graph labeling, that enable them to be tested with a fixed number of tests irrespective of their size. The approach is novel as it also greatly simplifies the processes of on-chip test vector generation and response comparison that are necessary for built-in self-test. Each circuit module is tested in a pseudo-exhaustive manner with deterministic as opposed to random test sequences. This results in a comprehensive test of the circuit for which built-in self-test is designed.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00135230
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 16
    Electronic Resource
    Electronic Resource
    Differential fault simulation for sequential circuits (1990)
    Springer
    Journal of electronic testing 1 (1990), S. 7-13 
    Details
    ISSN: 1573-0727
    Keywords: fault simulation ; sequential circuits ; test generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A new fast fault simulation algorithm called differential fault simulation, DSIM, for synchronous sequential circuits is described. Unlike concurrent fault simulation, for every test vector, DSIM simulates the good machine and each faulty machine separately, one after another, rather than simultaneously simulating all machines. Therefore, DSIM dramatically reduces the memory requirement and the overhead in the memory management in concurrent fault simulation. Also, unlike serial fault simulation, DSIM simulates each machine by reprocessing its differences from the previously simulated machine. In this manner, DSIM is more efficient than serial fault simulation. Experiments have shown that DSIM runs 3 to 12 times faster than an existing concurrent fault simulator. In addition, owing to the simplicity of this algorithm, DSIM is very easy to implement and maintain. An implementation consists of only about 300 lines of “C” language statements added to the event-driven true-value simulator in an existing sequential circuit test generator program, STG3. Currently DSIM uses the zero-delay timing model. The addition of alternative delay models is under development.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00134011
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 17
    Electronic Resource
    Electronic Resource
    A hierarchical test generation methodology for digital circuits (1990)
    Springer
    Journal of electronic testing 1 (1990), S. 103-123 
    Details
    ISSN: 1573-0727
    Keywords: digital circuits ; fault modeling ; hierarchical testing ; high-level circuit models ; test generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00137388
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 18
    Electronic Resource
    Electronic Resource
    High-temperature properties of the Bi-Sr-Ca-Cu-O system: Simultaneous occurrence of melting, oxygen desorption, and a metal-insulator transition (1988)
    Springer
    Journal of superconductivity 1 (1988), S. 407-415 
    Details
    ISSN: 1572-9605
    Keywords: high-T c superconductivity ; resistivity ; melting ; oxygen desorption ; metal-insulator transition
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology , Physics
    Notes: Abstract We have investigated the temperature dependence of the electrical transport and the thermogravimetric properties, from -200°C to +1000Ć, of the Bi-Sr-Ca-Cu-O high-temperature superconductor. We conclude that this system has a cooperative, simultaneous-melting/oxygen desorption/metal-insulator transition that occurs near 900°C. We speculate on its nature and on its relationship to phenomena found in other high-T c superconductors.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00618597
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 19
    Electronic Resource
    Electronic Resource
    Thermoelectric power measurements of YBa2Cu3O7−δ up to 950°C and their application to test the band structure near EF (1988)
    Springer
    Journal of superconductivity 1 (1988), S. 53-61 
    Details
    ISSN: 1572-9605
    Keywords: YBa2Cu3O7−δ ; resistivity ; thermoelectric power
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology , Physics
    Notes: Abstract Four-probe resistivity (ρ) and thermoelectric power (TEP) measurements were carried out on samples of YBa2Cu3O7−δ up to 950°C, in air and in flowing oxygen at 1 bar. Below 700 K the TEP is small and increases rapidly above it, reaching, at 1200 K, +140μV/K in air and +120μV/K in oxygen. At the changeover temperature (700 K) the slope of logρ vs.T changes abruptly. These results are interpreted in terms of a model of transport of carriers in a narrow band, which is full forδ = 1 and half-filled forδ = 0. Possible origins for such a narrow band are discussed in detail.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00617951
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
  • 20
    Electronic Resource
    Electronic Resource
    Comparison of Y-Ba-Cu-O compounds prepared from BaCuO2 and Ba2Cu3O5+δ (1988)
    Springer
    Journal of superconductivity 1 (1988), S. 451-461 
    Details
    ISSN: 1572-9605
    Keywords: Y-Ba-Cu-O ; BaCuO2 ; Ba2Cu3O5+δ ; resistivity ; superconducting phases ; baseline hysteresis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology , Physics
    Notes: Abstract Series of Y-Ba-Cu-O compositions were prepared from barium cuprates and Y2O3, using a two-step synthesis route. It has been shown that Ba2Cu3O5+δ is essential in formation of the YBa2Cu3O7−δ superconducting phase while BaCuO2 is not an appropriate starting material. A wide composition range fromx=2 to 17 was prepared from Ba2Cu3O5+δ in the YBa x Cu1.5x O z series without disappearance of macroscopic superconductivity atT c〉77 K. Resistivity measurements hint at the existence of two superconducting phases. ESR investigations revealed a baseline hysteresis, depending on the actual value ofx.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00618601
    Location Call Number Expected Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
Close ⊗
This website uses cookies and the analysis tool Matomo. More information can be found here...