ALBERT

Description: One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.

Description: To avoid additional layers for high linearity capacitances in modern CMOS process families, compensated depletion mode MOS capacitances can be used. As shown in previous publications, these MOS capacitances are suitable for low voltage applications. But there exist limitations concerning the linearity of these capacitances. In this work, the impact of the nonlinearity of the capacitances on different kinds of circuits is investigated. Several examples will be discussed to show how to choose the right capacitance topology.

Description: One of the most challenging design issues for next generations of (mobile) communication systems is fulfilling the computational demands while finding an appropriate trade-off between flexibility and implementation aspects, especially power consumption. Flexibility of modern architectures is desirable, e.g. concerning adaptation to new standards and reduction of time-to-market of a new product. Typical target architectures for future communication systems include embedded FPGAs, dedicated macros as well as programmable digital signal and control oriented processor cores as each of these has its specific advantages. These will be integrated as a System-on-Chip (SoC). For such a heterogeneous architecture a design space exploration and an appropriate partitioning plays a crucial role. On the exemplary vehicle of a Viterbi decoder as frequently used in communication systems we show which costs in terms of ATE complexity arise implementing typical components on different types of architecture blocks. A factor of about seven orders of magnitude spans between a physically optimised implementation and an implementation on a programmable DSP kernel. An implementation on an embedded FPGA kernel is in between these two representing an attractive compromise with high flexibility and low power consumption. Extending this comparison to further components, it is shown quantitatively that the cost ratio between different implementation alternatives is closely related to the operation to be performed. This information is essential for the appropriate partitioning of heterogeneous systems.

Description: In diesem Beitrag wird ein Überblick ber transitionsmindernde Buskodierverfahren zur verlustleistungsminimierten Datenübertragung zwischen Modulen digitaler Systeme gegeben. Ein neues adaptives Verfahren, das Adaptive Minimum Weight Codes (AMWC) Verfahren wird vorgestellt, welches Datenworte auf einen Code mit minimalem Gewicht unter Nutzung dynamisch rekonfigurierbarer Codetabellen abbildet. Aufgrund der Anpassbarkeit der Kodiervorschrift benötigt es keine Kenntnis statistischer Parameter der zu übertragenden Datenströme und eignet sich deshalb insbesondere zur Kodierung von Datenströmen mit über der Zeit veränderlichen Parametern. Im Gegensatz zu anderen bislang publizieren adaptiven Verfahren, welche aufgrund ihres enormen Eigenverlustleistungsanteiles nicht effizient implementierbar sind, besitzt die Implementierung von AMWC einen geringeren Hardwareoverhead und verändert das Systembusinterface nicht. Der Beitrag stellt theoretische Grundlagen vor und gibt eine hardwareeffiziente Implementierung an. Experimentelle Untersuchungen ergaben eine Reduktion der Schaltaktivität um 38%.In this paper state-of-the-art transition-minimizing bus encoding schemes for power-efficient data transmission between modules of digital systems are summarized. A new adaptive scheme, the Adaptive Minimum Weight Codes (AMWC) is presented which maps data words unambiguously on a minimum weight code using dynamically reconfigurable code tables. Due to its adaptability our scheme does not require a priori knowledge about statistical parameters of data streams to be transmitted. Therefore it is especially suited for data streams with time-varying parameters. Unlike other adaptive techniques presented to date, which are infeasible to implement into hardware due to their tremendous overhead in self dissipated power, the implementation of our encoding technique requires less interface. The fundamentals of the encoding scheme and a hardware-efficient implementation are given. Experimental results showed a reduction in bus transition activity of up to 38%. hardware overhead and does not modify the system bus

Description: Feldvariable Kammern (FVK, engl.: modestirred- chamber) werden unter anderem für EMV-Störfestigkeitsprüfungen verwendet. Ein häufig genanntes Argument, das die Einführung dieser Kammern als normgerechte Prüfumgebung vorantreiben soll, ist eine hohe Feldstärke, die im Vergleich zu anderen Testumgebungen mit relativ moderaten HF-Leistungen erreicht werden kann. Besonders für sicherheitskritische Geräte, wie Komponenten aus der Avionik- oder KFZ-Industrie, sind heutzutage Testfeldstärken von mehreren 100 V/m notwendig. Derart hohe Feldstärken können in Umgebungen, die ein ebenes Wellenfeld erzeugen oder nachbilden, nur mit großen HFLeistungen generiert werden. Durch die Resonanzeigenschaften einer FVK können demgegenüber mit sehr viel weniger Leistung und damit Verstärkeraufwand vergleichbare Werte der Feldstärke erzeugt werden. Allerdings sinkt mit zunehmendem Volumen die erreichbare Feldstärke bei gleicher Speiseleistung. Idealerweise sollen Feldvariable Kammern bei möglichst niedrigen Frequenzen für EMVTests nutzbar sein, was jedoch ein großes Kammervolumen erfordert. Das Problem, bei niedrigen Frequenzen hohe Feldstärken erzeugen zu können, relativiert deshalb den Vorteil von FVKn gegenüber bekannten Testumgebungen bei niedrigen Testfrequenzen. Der Posterbeitrag erläutert, welche Feldstärken in verschieden großen Feldvariablen Kammern beim Einspeisen einer bestimmten hochfrequenten Leistung erreicht werden können. Anhand dieser Ergebnisse wird aufgezeigt, oberhalb welcher Grenzfrequenz eine Anwendung von FVKn nur sinnvoll erscheint. Mode-stirred chambers (MSCs) can be used for radiated immunity tests in EMC testing. Advantageous compared to conventional test methods is the high field strength which can here be generated with less RF-Power. This point is often the main argument for pushing the standardization of MSCs as an other EMC testing environment. Especially for safety-critical electronic equipment like avionic or automotive systems, immunity tests with field strengths of several 100 V/m are necessary. Such high field strengths can only be generated with substantial RF power and therefore expensive amplifiers if the test is performed in an environment with plane waves. Due to resonance effects in mode-stirred chambers, comparable values of the field strength can there be obtained with significantly less power. In these chambers the field strength declines with increasing volume for a constant input power. As an ideal testing environment a mode-stirred chamber should also work at low frequencies which requires a large volume, however. Hence there is a contradiction between generating high level field strengths on the one hand and obtaining a lowest usable frequency of several 10 MHz on the other. This relativizes the advantage of generating high field strengths with less power if the chamber is supposed to work down to low frequencies. This article deals with the field strengths that can be obtained in mode-stirred chambers with a certain size. Data of different mode-stirred chambers are compared. From this a frequency limit can be derived, above which the use a mode-stirred chamber for achieving high field strengths seems meaningful only.

Description: In modernen CMOS-Technologien werden die Verzögerungszeit, die Ausgangsflankensteilheit und der Querstrom eines Gatters sowohl durch die Lastkapazität als auch durch die Steilheit des Eingangssignals beeinflusst. Die heute verwendeten Technologiebibliotheken beinhalten Tabellenmodelle mit 25 oder mehr Stützpunkten dieser Abhängigkeiten, woraus durch Interpolation die benötigten Zwischenwerte berechnet werden. Bisherige Versuche, analytische Modelle abzuleiten beruhten darauf, den Querstrom zu vernachlässigen oder Transistorströme als stückweise linear anzunähern. Der hier gezeigte Ansatz beruht auf einer näherungsweisen Lösung der Differentialgleichung, die aus den beiden Transistorströmen und einer Lastkapazität besteht und damit das Schaltverhalten eines Inverters beschreibt. Mit wenigen Technologieparametern können daraus für einen beliebig dimensionierten Inverter die für eine Timing- und Verlustleistungsanalyse notwendigen Größen berechnet werden. Das Modell erreicht bei einem Vergleich zu Referenzwerten aus SPICE Simulationen eine Genauigkeit von typischerweise 5%.In modern CMOS-technologies the gate delay, output transition time and the short-circuit current depend on the capacitive load as well as on the input transition time. Today’s technology libraries use table models with 25 or more samples for these dependencies. Intermediate values have to be calculated through interpolation. Attempts to derive analytical models are based on neglecting the short-circuit current or approximating it by piecewise linear functions. The approach shown in this paper provides an approximate solution for the differential equation describing the dynamic behavor of an inverter circuit. It includes the influence of both transistor currents and a single load capacitance. The required values for timing and power analysis can be calculated with a small set of technology parameters for an arbitrary designed inverter. Compared to reference values extracted from SPICE simulations, the model achieves a typical precision of 5%.

Description: This letter presents organic thin-film-transistors (OTFT) using the small organic molecule Pentacene targeting applications like radio controlled identification tags. Simple OTFTs as well as inverter circuits based on a pconducting silicon wafer substrate are presented. Comparing PECVD oxide and LTO as dielectric, only LTO deposited layers provide sufficient electrical stability. PECVD oxides show defects called “pin-holes", leading to short circuiting through the gate dielectrics. OTFTs of L=1µm/W=1000µm were prepared providing Ids = 61µA at –40Vds and –40Vgs, a subthreshold slope of 10.3 V/dec and an on-offratio of 102. The inverter circuits using insulated gate contacts switch from VA=–10V to VA=–3V output voltage when the input voltage is varied from VE=0V to VE=–8V at a supplied voltage of VB=–10V.

Description: Various reasons like technology progress, flexibility demands, shortened product cycle time and shortened time to market have brought up the possibility and necessity to integrate different architecture blocks on one heterogeneous System-on-Chip (SoC). Architecture blocks like programmable processor cores (DSP- and GPP-kernels), embedded FPGAs as well as dedicated macros will be integral parts of such a SoC. Especially programmable architecture blocks and associated optimization techniques are discussed in this contribution. Design space exploration and thus the choice which architecture blocks should be integrated in a SoC is a challenging task. Crucial to this exploration is the evaluation of the application domain characteristics and the costs caused by individual architecture blocks integrated on a SoC. An ATE-cost function has been applied to examine the performance of the aforementioned programmable architecture blocks. Therefore, representative discrete devices have been analyzed. Furthermore, several architecture dependent optimization steps and their effects on the cost ratios are presented.

Description: In modern communication, sensor and signal processing systems digitisation methods are gaining importance. They allow for building software configurable systems and provide better stability and reproducibility. Moreover digital front-ends cover a wider range of applications and have better performance compared with analog ones. The quest for new architectures in radio frequency front-ends is a clear consequence of the ever increasing number of different standards and the resulting task to provide a platform which covers as many standards as possible. At microwave frequencies, in particular at frequencies beyond 10 GHz, no direct sampling receivers are available yet. A look at the roadmap of the development of commercial analog-to-digital-converters (ADC) shows clearly, that they can neither be expected in near future. We present a novel architecture, which is capable of direct sampling of band-limited signals at frequencies beyond 10 GHz by means of an over-sampling technique. The wellknown Nyquist criterion states that wide-band digitisation of an RF-signal with a maximum frequency ƒ requires a minimum sampling rate of 2 · ƒ . But for a band-limited signal of bandwidth B the demands for the minimum sampling rate of the ADC relax to the value 2 · B. Employing a noise-forming sigma-delta ADC architecture even with a 1-bit-ADC a signal-to-noise ratio sufficient for many applications can be achieved. The key component of this architecture is the sample-and-hold switch. The required bandwidth of this switch must be well above 2 · ƒ . We designed, fabricated and characterized a preliminary demonstrator for the ISM-band at 2.4 GHz employing silicon Schottky diodes as a switch and SiGe-based MMICs as impedance transformers and comparators. Simulated and measured results will be presented.

Description: For the widespread 12-term TMSO and LMSO calibration of 4-sampler vector network analyzers (VNA), the sensitivity coefficients of the S-parameters of two-ports are developed as functions of the deviations of the reflection coefficients of the one-port calibration standards and of an imperfect through or line connection. Expressions representing the deviations of the S-parameters with respect to the error terms and for the deviations of the error terms with respect to the non-ideal calibration standards are also given. It is shown that the deviations of the S-parameters become quite large particularly for high-reflective two-port test objects. If applying a broadband load (instead of using the time consuming “ideal" sliding load routine) and the VNA-internal firmware-operated calibration and evaluation routines where the reflection coefficient is set to zero, deviations may appear of some 0,1 dB for the attenuation and some degrees of the transmission phase angle.