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  • Electrical Engineering, Measurement and Control Technology  (16)
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  • Articles  (16)
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  • Electrical Engineering, Measurement and Control Technology  (16)
  • 1
    Electronic Resource
    Electronic Resource
    A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing (1999)
    Springer
    Journal of electronic testing 15 (1999), S. 87-96 
    Details
    ISSN: 1573-0727
    Keywords: design-for-testability ; BIST ; scan design
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper introduces a new multi-mode scannable memory element which allows pseudorandom testing to be integrated with scan in sequential circuits without the need of any design changes. As in the case of scan, the new element is used in place of regular flip-flops in the design library. Concurrent with normal operation, the design can accumulate a signature of the state variables in the scan-register configured as a multiple input signature analyzer (MISA). Thus virtually complete state observability is achieved without the need of scanning-out the state for each test-input. The pseudorandom states of the MISA can also be utilized as state inputs in pseudorandom testing. In this way, most faults are covered in a pseudorandom, “test per clock” mode. Only a few random pattern resistant faults require scan, greatly reducing test application time. Pseudorandom delay testing of the true normally active circuit paths is also possible. Two-pattern tests are supported. Finally, we show that the new memory element can also be used for fault-tolerant design.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008328101088
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  • 2
    Electronic Resource
    Electronic Resource
    Deterministic Built-in Pattern Generation for Sequential Circuits (1999)
    Springer
    Journal of electronic testing 15 (1999), S. 97-114 
    Details
    ISSN: 1573-0727
    Keywords: BIST ; Comma coding ; embedded-core testing ; Huffman coding ; pattern decoding ; run-length encoding ; sequential circuit testing ; statistical encoding
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract We present a new pattern generation approach for deterministic built-in self testing (BIST) of sequential circuits. Our approach is based on precomputed test sequences, and is especially suited to sequential circuits that contain a large number of flip-flops but relatively few controllable primary inputs. Such circuits, often encountered as embedded cores and as filters for digital signal processing, are difficult to test and require long test sequences. We show that statistical encoding of precomputed test sequences can be combined with low-cost pattern decoding to provide deterministic BIST with practical levels of overhead. Optimal Huffman codes and near-optimal Comma codes are especially useful for test set encoding. This approach exploits recent advances in automatic test pattern generation for sequential circuits and, unlike other BIST schemes, does not require access to a gate-level model of the circuit under test. It can be easily automated and integrated with design automation tools. Experimental results for the ISCAS 89 benchmark circuits show that the proposed method provides higher fault coverage than pseudorandom testing with shorter test application time and low to moderate hardware overhead.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008384201996
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  • 3
    Electronic Resource
    Electronic Resource
    Decentralized BIST Methodology for System Level Interconnects (1999)
    Springer
    Journal of electronic testing 15 (1999), S. 255-265 
    Details
    ISSN: 1573-0727
    Keywords: interconnect ; boundary scan ; BIST ; DFT
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper presents an architecture for the local generation of global test vectors for interconnects in a multiple scan chain environment. A unified BIST module is inserted as the gateway for each scan chain to transform the hierarchy of backplane, boards, and scan chains into a one-dimensional array of scan chains. The BIST modules are identical for all the scan chains except for the programmable personalized memories. The personalized memory contains a scan stage type table for the test generation, response compression, and driver contention avoidance. It also contains a scan chain identification number which serves as the seed for the generation of globally distinct serial vectors. The proposed methodology achieves 100% coverage on stuck-at and short faults.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008336824268
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  • 4
    Electronic Resource
    Electronic Resource
    Built-in Self Test Based on Multiple On-Chip Signature Checking (1999)
    Springer
    Journal of electronic testing 14 (1999), S. 227-244 
    Details
    ISSN: 1573-0727
    Keywords: BIST ; multiple signature comparison testing ; aliasing probability
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract We propose an improved BIST architecture which supports on-chip comparison of signatures at no significant increase in area. The proposed test architecture reduces detection latency and eliminates the lengthy scan-out phase from each test session by allowing testing and on-chip signature comparison of multiple intermediate signatures to occur concurrently. The work is based on a novel procedure to implement the multiple on-chip signature checking. We show that such a test method gives significant improvements in test application time and aliasing probability. This paper also presented two techniques to minimize the test area overhead with a very small test time overhead compare to the conventional schemes. These techniques resulted in up to 80% savings in test area overhead for some High-level synthesis benchmark circuits. This paper also presents an aliasing analysis of the proposed scheme.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008310203790
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  • 5
    Electronic Resource
    Electronic Resource
    Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits (1999)
    Springer
    Journal of electronic testing 14 (1999), S. 259-272 
    Details
    ISSN: 1573-0727
    Keywords: partial reset ; sequential circuit BIST ; BIST ; built0in self-test ; fault propagation analysis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Partial reset has been shown to have significant impact on test generation for sequential circuits in a stored-pattern test application environment. In this paper, we explore the use of partial reset in fault-independent testing and built-in self-test (BIST) of non-scan sequential circuits. We select a subset of flip-flops in the circuit to be resetable to logic one or zero during the application of the test vectors. The resetting is performed with random frequency. The selection of the flip-flops and the reset polarity is based on fault-propagation analysis, which determines the impact of a selected flip-flop on fault propagation from the circuits structure. Application of partial reset as described above yields an average improvement of 15% in fault-coverage for sequential circuits resistant to random pattern testing. To further enhance testability, we also present a methodology for selecting observable test points based on propagation of switching activity. Overall, high fault coverages (about 97%) are obtained for many of the ISCAS89 benchmark circuits. Thus, partial reset BIST provides a low cost alternative for testing sequential circuits when scan design is unacceptable due to area and/or delay constraints. The routing overhead for implementing BIST is seen to be about 6%.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008366304699
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  • 6
    Electronic Resource
    Electronic Resource
    A Scan-BIST Structure to Test Delay Faults in Sequential Circuits (1999)
    Springer
    Journal of electronic testing 14 (1999), S. 95-102 
    Details
    ISSN: 1573-0727
    Keywords: delay faults ; scan design ; BIST
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Delay testing that requires the application of consecutive two-pattern tests is not an easy task in a scan-based environment. This paper proposes a novel approach to the delay fault testing problem in scan-based sequential circuits. This solution is based on the combination of a BIST structure with a scan-based design to apply delay test pairs to the circuit under test.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008305507376
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  • 7
    Electronic Resource
    Electronic Resource
    BISTing Datapaths under Heterogeneous Test Schemes (1999)
    Springer
    Journal of electronic testing 14 (1999), S. 115-123 
    Details
    ISSN: 1573-0727
    Keywords: RT level ; BIST ; datapath ; test synthesis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract In this paper, we present a fast and efficient algorithm for BISTing datapaths described at the Register Transfer (RT) level. This algorithm is parameterized by user defined tuning factors allowing tradeoffs between fault coverage, area overhead and test application time. This algorithm is generic in the sense it handle and mixes heterogeneous test pattern generators and compactors.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008309625123
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  • 8
    Electronic Resource
    Electronic Resource
    Testability Enhancement for Control-Flow Intensive Behaviors (1998)
    Springer
    Journal of electronic testing 13 (1998), S. 239-257 
    Details
    ISSN: 1573-0727
    Keywords: test synthesis ; behavioral testability analysis and insertion ; BIST
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A BIST-based test synthesis methodology for control-flow intensive behaviors is proposed. This methodology targets the control statements in a behavioral description, such as if-then-else and loop statements, because such statements can introduce testability problems in the resulting circuit. How well the operations in each branch of a control statement can be tested depends on the probability of taking each branch and the quality of the test patterns used in each branch. Behavioral modifications are presented that can resolve these testability issues. The proposed methodology systematically identifies poor testability areas within a behavior and applies the behavioral modifications to improve the testability. Experimental results from six practical examples show that this technique is effective.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008381718989
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  • 9
    Electronic Resource
    Electronic Resource
    Integrated Temperature Sensors for On-Line Thermal Monitoring of Microelectronic Structures (1998)
    Springer
    Journal of electronic testing 12 (1998), S. 93-99 
    Details
    ISSN: 1573-0727
    Keywords: temperature sensor ; thermal monitoring ; on-line testing ; BIST ; oscillation-test strategy
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Built-in temperature sensors increase the system reliability by predicting eventual faults caused by excessive chip temperatures. In this paper, simple and efficient built-in temperature sensors for the on-line thermal monitoring of microelectronics structures are introduced. The proposed temperature sensors produce a signal oscillating at a frequency proportional to the temperature of the microelectronics structure and therefore they are compatible to the oscillation-test method. The oscillation-test method is a low-cost and robust test method for mixed-signal integrated circuits based on transforming the circuit under test (CUT) to an oscillator. This paper presents the design and detailed characteristics of the sensors proposed based on the CMOS 1.2 µm technology parameters of Mitel S.C.C. Extensive post-layout simulations show that the oscillation frequency is very sensitive to temperature variations. The sensors proposed require very small power dissipation and silicon area.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008285907945
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  • 10
    Electronic Resource
    Electronic Resource
    Mixed-Mode BIST Using Embedded Processors (1998)
    Springer
    Journal of electronic testing 12 (1998), S. 127-138 
    Details
    ISSN: 1573-0727
    Keywords: BIST ; random pattern testing ; deterministic BIST ; embedded systems
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not completely random pattern testable, the test programs have to generate deterministic patterns after random testing. Usually the random test part of the program requires long run times whereas the part for deterministic testing has high memory requirements. In this paper it is shown that an appropriate selection of the random pattern test method can significantly reduce the memory requirements of the deterministic part. A new, highly efficient scheme for software-based random pattern testing is proposed, and it is shown how to extend the scheme for deterministic test pattern generation. The entire test scheme may also be used for implementing a scan based BIST in hardware.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008294125692
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  • 11
    Electronic Resource
    Electronic Resource
    On-Chip Weighted Random Patterns (1998)
    Springer
    Journal of electronic testing 13 (1998), S. 41-50 
    Details
    ISSN: 1573-0727
    Keywords: LSSD ; SRL ; BIST ; WRP ; signal probability ; detection probability
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Even though there has been a considerable effort in proposing weighted random pattern testing schemes over the years, insufficient attention has been devoted to their implementation. This paper describes the design details, operation, cost, and performance of a distributed weighted pattern test approach at the chip level. The traditional LSSD SRLs are being replaced by WRP SRLs designed specifically to facilitate a weighted random pattern (WRP) test. A two-bit code is transmitted to each WRP SRL to determine its specific weight. The WRP test is then divided into groups, where each group is activated with a different set of weights. The weights are dynamically adjusted during the course of the test to “go after” the remaining untested faults. The cost and performance of this design system are explored on ten pilot chips. Results of this experiment are provided in the paper.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008385116436
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  • 12
    Electronic Resource
    Electronic Resource
    Behavioral Testability Insertion for Datapath/Controller Circuits (1997)
    Springer
    Journal of electronic testing 11 (1997), S. 9-28 
    Details
    ISSN: 1573-0727
    Keywords: test synthesis ; behavioral testability analysis ; BIST
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A method for test synthesis in the behavioral domain is described.The approach is based on the notion of adding a test behavior to the normal-mode design behavior. This testbehavior describes the behavior of the design in test mode. Thenormal-mode design behavior and test-mode test behavior are combinedand then synthesized by any general-purpose synthesis system toproduce a testable design with inserted BIST structures. The testbehavior is derived from the design behavior using testabilityanalysis based on metrics that quantify the testability of signalsand variables embedded within behaviors. The insertion method iscombined with a behavioral test scheme thatintegrates a) the design controller and test controller, b) testingof the entire datapath and controller. Examples show that when thetestability insertion procedure is used to modify a behavior beforesynthesis, the resulting synthesized physical implementation isindeed more easily tested than an implementation synthesized directlyfrom the original behavior.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008291616071
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  • 13
    Electronic Resource
    Electronic Resource
    Incorporating I DDQ Testing with BIST for Improved Coverage: An Experimental Study (1997)
    Springer
    Journal of electronic testing 11 (1997), S. 147-156 
    Details
    ISSN: 1573-0727
    Keywords: I DDQ ; BIST ; fault coverage ; open faults ; built in current sensor ; BICS
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract In this paper we present an experimental study on the effectivenessof incorporating at-speed I DDQ testing with traditionalBIST for improved test coverage. The high speed I DDQtesting is conducted using the differential built-in on-chip current sensor(BICS) that we have recently developed. Two test chips were designed andfabricated implementing a CMOS version of the 74181 ALU chip. In copies ofthis circuit we included the capability of activating 45 different“realistic” CMOS faults: inter- and intra-layer shorts andopens. We examine the fault coverage of both Boolean (voltage) testing andI DDQ testing for these realistic faults. An interestingfinding of our study is that I DDQ testing also detectedseveral of the open faults. Moreover, these include precisely those openfaults for which two pattern voltage tests can get invalidated because oftransient switching states. Our results show that combining both Boolean andcurrent testing does enhance test coverage in a BIST environment.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008218422533
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  • 14
    Electronic Resource
    Electronic Resource
    Fault-based testing and diagnosis of balanced filters (1996)
    Springer
    Analog integrated circuits and signal processing 11 (1996), S. 5-19 
    Details
    ISSN: 1573-1979
    Keywords: balanced filters ; analogue ; BIST ; fault diagnosis ; ATPG
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract The test and diagnosis of fully differential analogue filters are addressed in this paper. Full coverage of hard/soft faults affecting circuit behaviour can be achieved by adjusting the tolerance window of the built-in self-test circuitry and the amplitude and frequency of the input test signal. Under a single fault assumption, the faulty active or passive component is located and the actual defective value of a faulty passive component is determined. A test generation procedure which results in maximum fault coverage and maximal diagnosis of hard/soft faults in the filter is presented. The test and diagnosis approach can be made compatible with IEEE Std 1149.1 for boundary scan testing.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00174235
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  • 15
    Electronic Resource
    Electronic Resource
    Efficient UBIST implementation for microprocessor sequencing parts (1995)
    Springer
    Journal of electronic testing 6 (1995), S. 295-312 
    Details
    ISSN: 1573-0727
    Keywords: self-checking circuits ; totally self-checking circuits ; strongly code disjoint checkers ; BIST ; LFSR ; signature analyser ; UBIST ; microprocessor sequencing part
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract In this paper we first present an improved self-checking solution for the sequencing part of the Motorola MC 68000 microprocessor. compared to previous self-checking proposals for this microprocessor, the present scheme decreases the area overhead and simplifies the complexity of both functional circuits and checkers. In addition, the unified BIST method introduced recently, is applied to this scheme. This method uses a merging of self-checking and BIST techniques and allows a high fault coverage for all tests needed for the integrated circuits, e.g. off-line test for fabrication faults and for maintenance, and on-line concurrent error detection in the field.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00996438
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  • 16
    Electronic Resource
    Electronic Resource
    Avoiding linear dependencies in LFSR test pattern generators (1995)
    Springer
    Journal of electronic testing 6 (1995), S. 229-241 
    Details
    ISSN: 1573-0727
    Keywords: ATPG ; BIST ; characteristic polynomials ; LFSR ; pseudo-random testing
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Linear Feedback Shift Registers (LFSRs) constitute a very efficient mechanism for generating pseudoexhaustive or pseudo-random test sets for the built-in self-testing of digital circuits. However, a well-known problem with the use of LFSRs is the occurrence of linear dependencies in the generated patterns. In this paper, we show for the first time that the amount of linear dependencies can be controlled by selecting appropriate characteristic polynomials and reordering the LFSR cells. We identify two classes of such polynomials which, by appropriate LFSR cell ordering, guarantee that a large ratio of linear dependencies cannot occur. Experimental results show significant enhancements on the fault coverage for pseudo-random testing and support the theoretical relation between minimization of linear dependencies and effective fault coverage.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00993089
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