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  • Articles  (13)
  • CMOS  (13)
  • Springer  (13)
  • National Academy of Sciences
  • 2015-2019
  • 1995-1999  (13)
  • 1975-1979
  • Electrical Engineering, Measurement and Control Technology  (13)
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  • Articles  (13)
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Keywords
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  • Springer  (13)
  • National Academy of Sciences
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  • Electrical Engineering, Measurement and Control Technology  (13)
  • 1
    Electronic Resource
    Electronic Resource
    A 16 × 16 Cellular Neural Network Universal Chip: The First Complete Single-Chip Dynamic Computer Array with Distributed Memory and with Gray-Scale Input-Output (1998)
    Springer
    Analog integrated circuits and signal processing 15 (1998), S. 227-237 
    Details
    ISSN: 1573-1979
    Keywords: CNN ; CNN universal chip ; computer array ; CMOS ; analog ; nonlinear dynamics
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper presents a 16 × 16 Cellular Neural Network Universal Chip with analog input and output ports, which can read in and process gray-scale images in the analog domain. The chip contains about 5,000 analog multipliers and has been fabricated in a 0.8 µm CMOS process.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008278225960
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  • 2
    Electronic Resource
    Electronic Resource
    DPAD2—A Field Programmable Analog Array (1998)
    Springer
    Analog integrated circuits and signal processing 17 (1998), S. 67-89 
    Details
    ISSN: 1573-1979
    Keywords: analog field array ; CMOS
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract DPAD2 is a Field Programmable Analog Array (FPAA) based on CMOS switched capacitor technology. This paper describes the major design decisions that went into creating DPAD2 with respect to the ultimate goal of the work, being a mixed signal field programmable silicon solution. Two major compromises exist in the design of an FPAA, one between flexibility and performance, the other between functionality and die size; DPAD2 overcomes the first with a novel field programmable hierarchic routing scheme and the second by careful analysis of many disparate designs to arrive at a best compromise solution. Results from prototype silicon are presented where a single analog cell is reconfigured to perform a number of different analog signal processing functions. Bandwidth of the DPAD2 device is 500 kHz and the SNR is typically 60 dB, although both are application dependent. Introduction of the FPAA now enables a designer to have working silicon within one day, by a simple configuration of the silicon chip via a PC parallel interface. Software libraries of analog circuits are provided and allow very rapid creation of large and complex analog circuits.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008245831501
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  • 3
    Electronic Resource
    Electronic Resource
    An Inductorless 300 MHz Wideband CMOS Power Amplifier (1999)
    Springer
    Analog integrated circuits and signal processing 21 (1999), S. 57-65 
    Details
    ISSN: 1573-1979
    Keywords: CMOS ; RF ; power amplifier ; wideband ; inductorless
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract The power amplifier tends to be one of the most demanding parts to fully integrate when building an entire radio on a CMOS chip. In this paper the design of a fully integrated RF power amplifier without inductors is described. As inductors in CMOS technology are associated with various problems, it is interesting to examine what performance can be achieved without them. An amplifier with an operating band from 60 MHz to 300 MHz (−3 dB) is built in 0.8 μm CMOS. A 3 V supply is used. The measured midband power gain is 30 dB with 50 Ω resistive source and load impedance. As linearity is important for many modern modulation schemes, the amplifier is designed to be as linear as possible. The measured third order intercept point is 23 dBm and the 1 dB compression point is 10 dBm, both referred to the output. The output is single ended to avoid an off-chip differential to single ended transformer.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008327810923
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  • 4
    Electronic Resource
    Electronic Resource
    Partial positive feedback for gain enhancement of low-power CMOS otas (1995)
    Springer
    Analog integrated circuits and signal processing 8 (1995), S. 21-35 
    Details
    ISSN: 1573-1979
    Keywords: CMOS ; amplifier ; low-power ; gain enhancement ; positive feedback
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Four circuit schemes that use partial positive feedback for gain enhancement in CMOS OTAs are examined. These circuit schemes are classified as type I and type II circuits. Type I circuits use a differential input pair with positive feedback and type II circuits use a active load with positive feedback. As the primary emphasis of these circuits is for micropower operation, the circuits have been examined in detail in the subthreshold region. A comparison of the primary characteristics of these circuits together with simulation results are presented. It is shown that partial positive feedback is a viable technique to increase the gain and the bandwidth of CMOS OTAs. Without any increase in power, a 20 dB increase in gain and a 5X improvement in bandwidth is feasible.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF01239377
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  • 5
    Electronic Resource
    Electronic Resource
    A linear CMOS transconductance element of an adaptively biased source-coupled differential pair using a quadritail cell (1996)
    Springer
    Analog integrated circuits and signal processing 11 (1996), S. 129-135 
    Details
    ISSN: 1573-1979
    Keywords: adaptive-biasing ; quadritail cell ; OTA ; CMOS
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A novel circuit design technique for realizing a linear CMOS transconductance element, consisting of an adaptively biased source-coupled differential pair using a quadritail cell, is proposed. In the circuitry, the quadritail cell, which provides an output current proportional to the square of a differential input voltage, cancels a nonlinear term of the source-coupled differential pair. The circuit have a superior linearity and a wide linear input voltage range compared with the conventional linear CMOS transconductance elements because the transconductance characteristic is theoretically linear over wide input voltage range when all the MOS field-effect transistors (MOSFETs) are operating in the saturation region and the MOSFETs' behaviors are according to the relation based on the square-law characteristic. The proposed adaptively biased source-coupled differential pair was verified by using transistor-arrays and discrete components on a breadboard.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00174247
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  • 6
    Electronic Resource
    Electronic Resource
    A Locally Adaptive Multimode Photodetector Circuit (1999)
    Springer
    Analog integrated circuits and signal processing 18 (1999), S. 255-275 
    Details
    ISSN: 1573-1979
    Keywords: photodetection circuits ; CMOS ; vision ; imagers ; CCD ; Active Pixel Sensors (APS)
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Photodetection circuits form the first stage of the artificial image acquisition process. The image acquisition circuits discussed in this paper pertain to circuits fabricated in a standard CMOS process. Such circuits offers advantages such as random access to a pixel, faster readout, integration of processing circuitry on the same die, low voltage and low power dissipation, and lower cost over the conventional Charge Coupled Device (CCD) process. We describe a new locally adaptive multimode photodetector circuit. The advantages of the circuit are local adaptation, wide dynamic range, excellent sensitivity, and large output voltage swing. The circuit was fabricated in the 2μ CMOS process through MOSIS. Simulation and experimental results of the circuit are given.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008371624830
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  • 7
    Electronic Resource
    Electronic Resource
    A 220-MSample/s CMOS Sample-and-Hold Circuit Using Double-Sampling (1999)
    Springer
    Analog integrated circuits and signal processing 18 (1999), S. 21-31 
    Details
    ISSN: 1573-1979
    Keywords: sample-and-hold ; CMOS ; double-sampling ; high-speed
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A fully differential sample-and-hold (S/H) circuit using double-sampling is presented. Compared to a conventional S/H configuration with a similar opamp the double-sampling gives a factor of two increase in the sampling rate while maintaining comparable power consumption. The circuit is designed in a 0.5 μm CMOS technology. The measurements show 10-bit operation up to the Nyquist frequency at the sampling rate of 220 MS/s with 25 mW @ 3 V power dissipation.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008395201974
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  • 8
    Electronic Resource
    Electronic Resource
    An 8 Bit Current-Mode CMOS A/D Converter with Three Level Folding Amplifiers (1999)
    Springer
    Analog integrated circuits and signal processing 20 (1999), S. 139-143 
    Details
    ISSN: 1573-1979
    Keywords: CMOS ; three level folding amplifier ; current-mode ; A/D converter
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract An 8 bit current-mode folding and interpolation analog to digital converter (ADC) with three-level folding amplifiers is proposed in this paper. A current-mode three-level folding amplifier is employed not only to reduce the number of reference current sources, but also to decrease a power dissipation within the ADC. The designed ADC fabricated by a 0.8 μm n-well CMOS double metal/single poly process occupies the chip area of 2.2 × 1.6. The experimental result shows the power dissipation of 33.6 mW with a power supply of 5 V.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008350413299
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  • 9
    Electronic Resource
    Electronic Resource
    Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults (1995)
    Springer
    Journal of electronic testing 6 (1995), S. 7-22 
    Details
    ISSN: 1573-0727
    Keywords: Bridging fault ; checker ; CMOS ; self-checking circuits ; testability
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This work presents a design technique for CMOS static and dynamic checkers (to be used in self-checking circuits), that allows the detection of all internal single transistor stuck-on and bridging faults causing unacceptable degradations of the circuit dynamic performance (but not logical errors). Such a technique exploits simple voltage detector circuits to make sure that the intermediate faulty voltages inevitably produced by the faults of interest are always propagated at the checker output as logic errors. With the use of our technique, the main disadvantages of static checkers, so far preventing their use in practical applications, are overcome. The method has been applied to the particular case of two-rail (static as well as dynamic) checkers and its validity has been verified by means of electrical level simulations.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00993127
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  • 10
    Electronic Resource
    Electronic Resource
    A Novel Class AB CMOS Power Amplifier (1997)
    Springer
    Analog integrated circuits and signal processing 12 (1997), S. 49-58 
    Details
    ISSN: 1573-1979
    Keywords: power amplifier ; CMOS ; audio ; high efficiency ; low-voltage
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A novel class AB design is described. To achieve a large output voltage swing and to avoid the offset problems associated with a class AB input stage, the non-linearity is placed between the input and the output stage. Before the output stage the signal is separated in one positive and one negative half, which are then amplified separately. For the first time this topology is used in an integrated CMOS power amplifier. It operates with +/ −2.5 V supplies and can drive more than 4 Vpp into an 8 ω load.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1013278801558
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  • 11
    Electronic Resource
    Electronic Resource
    Analog Circuit Design Methodology in a Low Power RISC Microprocessor (1999)
    Springer
    Analog integrated circuits and signal processing 20 (1999), S. 85-94 
    Details
    ISSN: 1573-1979
    Keywords: microprocessor ; TLB ; CAM ; 0.35 μm ; CMOS
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract There are various kinds of analog CMOS circuits in microprocessors. IOs, clock distribution circuits including PLL, memories are the main analog circuits. The circuit techniques to achieve low power dissipation combined with high performance in newest prototype chip in the Super H RISC engines are described. A TLB delay can be decreased by using a CAM with a differential amplifier to generate the match signal. The accelerator circuit also helps to speed up the TLB circuit, enabling single-cycle operation. A fabricated 96-mm2 test chip with the super H architecture using 0.35-μm four metal CMOS technology is capable of 167-MHz operation at 300 Dhrystone MIPS with 2.0-W power dissipation.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008338110573
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  • 12
    Electronic Resource
    Electronic Resource
    An Analog Self-Test Based on Differential I DD Monitoring Supported by Differential I OUT Checking (1999)
    Springer
    Analog integrated circuits and signal processing 21 (1999), S. 33-44 
    Details
    ISSN: 1573-1979
    Keywords: analog circuits ; analog self-test ; dynamic I DD monitoring ; VLSI ; CMOS ; ASIC
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This paper proposes a novel DFT scheme that combines two test techniques—differential power supply current (ΔI DD ) monitoring and differential output current (ΔI OUT ) checking—in a single analog self-test. The DFT scheme is aimed at fully differential analog circuits. Fault detection is provided by means of differential measurement of the on-chip parameters, such as the I DD and I OUT currents. Due to the differential nature of the test principle used, no reference measurement is required prior to the test, thus the fault detection exhibits a significantly reduced dependency on process parameter variations, variation of temperature during the test as well as outside interference's. Based on measurement results, the realistic tolerance band for fault detection was determined and the fault coverage, resulting from previous simulation experiments, was adjusted.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008323710015
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  • 13
    Electronic Resource
    Electronic Resource
    CMOS PLL Design in a Digital Chip Environment (1997)
    Springer
    Analog integrated circuits and signal processing 14 (1997), S. 91-112 
    Details
    ISSN: 1573-1979
    Keywords: PLL ; CMOS ; mixed signal ; clock synthesis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract CMOS PLL‘s are becoming increasingly useful for clocksynthesis and recovery in CPU and other digital chip designs.However, the packaging and process are defined to meet the requirementsof the digital chip, not the analog portions of the PLL. Theenvironment defined by the digital requirements includes thepackage, the process and the dominant noise source. Packagesfor complex digital chips are larger and have more complex frequencyand signal integrity characteristics than smaller packages thatare appropriate for dedicated analog chips. Digital CMOS processeslack the quality capacitors, resistors and possible variety ofdevices that may be found in a process developed specificallyfor analog purposes. Digital switching causes significant noisethat dominates the spectrum that the circuit designer must worryabout. This paper considers a typical CMOS PLL design from thedigital chip design viewpoint.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008250912571
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