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  • United States  (286)
  • Earth Resources and Remote Sensing  (201)
  • Electronics and Electrical Engineering  (178)
  • 2000-2004  (665)
  • 1995-1999
  • 2004  (665)
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  • 2000-2004  (665)
  • 1995-1999
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  • 1
    Publication Date: 2019-08-28
    Description: An evolvable circuit includes a plurality of reconfigurable switches, a plurality of transistors within a region of the circuit, the plurality of transistors having terminals, the plurality of transistors being coupled between a power source terminal and a power sink terminal so as to be capable of admitting power between the power source terminal and the power sink terminal, the plurality of transistors being coupled so that every transistor terminal to transistor terminal coupling within the region of the circuit comprises a reconfigurable switch.
    Keywords: Electronics and Electrical Engineering
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  • 2
    Publication Date: 2019-08-28
    Description: A method for forming ferroelectric wafers is provided. A prestress layer is placed on the desired mold. A ferroelectric wafer is placed on top of the prestress layer. The layers are heated and then cooled, causing the ferroelectric wafer to become prestressed. The prestress layer may include reinforcing material and the ferroelectric wafer may include electrodes or electrode layers may be placed on either side of the ferroelectric layer. Wafers produced using this method have greatly improved output motion.
    Keywords: Electronics and Electrical Engineering
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  • 3
    Publication Date: 2019-08-28
    Description: Below is the 1st year progress report for NAG5-13435 "New Retrieval Algorithms for Geophysical Products from GLI and MODIS Data". Activity on this project has been coordinated with our NASA DB project NAG5-9604. For your convenience, this report has six sections and an Appendix. Sections I - III discuss specific activities undertaken during the past year to analyze/use MODIS data. Section IV formally states our intention to no longer pursue any research using JAXA's (formerly NASDA's) GLI instrument which catastrophically failed very early after launch (also see the Appendix). Section V provides some indications of directions for second year activities based on our January 2004 telephone discussions and email exchanges. A brief summary is given in Section VI.
    Keywords: Earth Resources and Remote Sensing
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  • 4
    Publication Date: 2019-08-27
    Description: A multi-sensor transducer and processing method allow insitu monitoring of the senor accuracy and transducer `health`. In one embodiment, the transducer has multiple sensors to provide corresponding output signals in response to a stimulus, such as pressure. A processor applies individual weight factors to reach of the output signals and provide a single transducer output that reduces the contribution from inaccurate sensors. The weight factors can be updated and stored. The processor can use the weight factors to provide a `health` of the transducer based upon the number of accurate versus in-accurate sensors in the transducer.
    Keywords: Electronics and Electrical Engineering
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  • 5
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    In:  Other Sources
    Publication Date: 2019-08-26
    Description: An assessment of the Airborne Visible/Infrared Imaging Spectrometer (AVIRIS) laboratory and in-flight uniformity is presented in this Slide presentation. The ideal uniform system is described, being a system where every spectrum is intercomparable to every other spectrum. Two types of failures to achieve this uniformity are described. Graphs showing measured spectral upwelling radiance, the expanded spectral convolution, the radiometric error from spectral error, the results from the hyperion Arizaro calibration experiment and a AVIRIS cross-track uniformity are among those presented. The reasons why uniformity matters are presented.
    Keywords: Earth Resources and Remote Sensing
    Type: AVIRIS Workshop; May 24, 2005 - May 27, 2005; California; United States
    Format: text
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  • 6
    Publication Date: 2019-08-24
    Description: Life-limiting processes in hollow cathodes are determined largely by the temperature of the emitter. To support development of cathode life models we have developed a noncontact temperature measurement technique which employs a stepper motor-driven fiber optic probe. The probe is driven inside the hollow cathode and collects light radiated by the hot interior surface of the emitter. Ratio pyrometry is used determine the axial temperature profile. Thermocouples on the orifice plate provide measurements ofthe external temperature during cathode operation and are used to calibrate the pyrometer system in situ with a small oven enclosing the externally heated cathode. Initial measurements of the temperature distribution in a hollow cathode with the same geometry as a cathode that failed after operating at 12 A emission current for 27800 hours are discussed.
    Keywords: Electronics and Electrical Engineering
    Type: AAIA Paper-2004-4116 , 40th AIAA/ASME/SAE/ASEE Joint Propulsion Conference and Exhibit; Jul 11, 2004 - Jul 14, 2004; Fort Lauderdale, FL; United States
    Format: text
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  • 7
    Publication Date: 2019-08-17
    Description: A DC motor is commutated by rotating a magnetic rotor to induce a magnetic field in at least one magnetostatic relay in the motor. Each relay is activated in response to the magnetic field to deliver power to at least one corresponding winding connected to the relay. In some cases, each relay delivers power first through a corresponding primary winding and then through a corresponding secondary winding to a common node. Specific examples include a four-pole, three-phase motor in which each relay is activated four times during one rotation of the magnetic rotor.
    Keywords: Electronics and Electrical Engineering
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  • 8
    Publication Date: 2019-08-17
    Description: According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.
    Keywords: Electronics and Electrical Engineering
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  • 9
    Publication Date: 2019-08-17
    Description: According to the invention, a digital design method for manipulating a digital circuit netlist is disclosed. In one step, a first netlist is loaded. The first netlist is comprised of first basic cells that are comprised of first kernel cells. The first netlist is manipulated to create a second netlist. The second netlist is comprised of second basic cells that are comprised of second kernel cells. A percentage of the first and second kernel cells are selection circuits. There is less chip area consumed in the second basic cells than in the first basic cells. The second netlist is stored. In various embodiments, the percentage could be 2% or more, 5% or more, 10% or more, 20% or more, 30% or more, or 40% or more.
    Keywords: Electronics and Electrical Engineering
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  • 10
    Publication Date: 2019-08-17
    Description: The present invention discloses a new family of switching amplifier classes called class E/F amplifiers. These amplifiers are generally characterized by their use of the zero-voltage-switching (ZVS) phase correction technique to eliminate of the loss normally associated with the inherent capacitance of the switching device as utilized in class-E amplifiers, together with a load network for improved voltage and current wave-shaping by presenting class-F.sup.-1 impedances at selected overtones and class-E impedances at the remaining overtones. The present invention discloses a several topologies and specific circuit implementations for achieving such performance.
    Keywords: Electronics and Electrical Engineering
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