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  • Articles  (3)
  • I DDQ  (3)
  • 1990-1994  (3)
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  • 1992  (3)
  • Electrical Engineering, Measurement and Control Technology  (3)
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  • Articles  (3)
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  • 1990-1994  (3)
  • 1985-1989
  • 1960-1964
  • 1950-1954
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  • 1992  (3)
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  • Electrical Engineering, Measurement and Control Technology  (3)
  • 1
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 3 (1992), S. 291-303 
    ISSN: 1573-0727
    Keywords: CMOS IC ; I DDQ ; Current testing ; IC quality ; defects ; fault models
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Quiescent power supply current (I DDQ ) testing of CMOS integrated circuits is a technique for production quality and reliability improvement, design validation, and failure analysis. It has been used for many years by a few companies and is now receiving wider acceptance as an industry tool. This article begins with a brief history of CMOS ICs to provide perspective on the origin of I DDQ testing. Next, the use of I DDQ testing for IC quality improvement through increased defect and fault detection is described. Then implementation issues are considered, including test pattern generation software, hardware instrumentation, limit setting, IC design guidelines, and defect diagnosis. An extended reference list is provided to help the reader obtain more information on specific aspects.
    Type of Medium: Electronic Resource
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  • 2
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 3 (1992), S. 327-335 
    ISSN: 1573-0727
    Keywords: I DDQ ; Gate oxide shorts ; reliability
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This is an application-oriented article on I DDQ to guide test engineers to a pragmatic method of implementing I DDQ . This article focuses on different aspects of I DDQ testing; quality, reliability, and test implementation. A description of I DDQ is presented, with different practical methods of implementing it, with empirical reliability data of I DDQ failures, and with empirical burn-in data identifying potential yield benefits. Employing I DDQ testing on digital CMOS technology, the user obtains a product with greater reliability. The data presented within this article, along with increasing customer focus on zero defects, clearly support I DDQ implementation.
    Type of Medium: Electronic Resource
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  • 3
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 3 (1992), S. 359-366 
    ISSN: 1573-0727
    Keywords: Current tests ; I DDQ ; logic tests ; test generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This article presents an approach to developing high quality tests for switch-level circuits using both current and logic test generation algorithms. Faults that are aborted or undetectable by logic tests may be detected by current tests, or vice versa. An efficient switch level test generation algorithm for generating current and logic tests is introduced. Clear definitions for analyzing the effectiveness of the joint test generation approach are derived. Experimental results are presented for demonstrating high coverage of stuck-at, stuck-on, and stuck-open faults for switch level circuits when both current and logic tests are used.
    Type of Medium: Electronic Resource
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