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  • Articles  (6)
  • I DDQ  (3)
  • I DDQ testing  (3)
  • 1990-1994  (6)
  • 1985-1989
  • 1960-1964
  • 1950-1954
  • 1992  (6)
  • Electrical Engineering, Measurement and Control Technology  (6)
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  • Articles  (6)
Source
Keywords
Publisher
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  • 1990-1994  (6)
  • 1985-1989
  • 1960-1964
  • 1950-1954
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  • Electrical Engineering, Measurement and Control Technology  (6)
  • 1
    Electronic Resource
    Electronic Resource
    I DDQ testing: A review (1992)
    Springer
    Journal of electronic testing 3 (1992), S. 291-303 
    Details
    ISSN: 1573-0727
    Keywords: CMOS IC ; I DDQ ; Current testing ; IC quality ; defects ; fault models
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Quiescent power supply current (I DDQ ) testing of CMOS integrated circuits is a technique for production quality and reliability improvement, design validation, and failure analysis. It has been used for many years by a few companies and is now receiving wider acceptance as an industry tool. This article begins with a brief history of CMOS ICs to provide perspective on the origin of I DDQ testing. Next, the use of I DDQ testing for IC quality improvement through increased defect and fault detection is described. Then implementation issues are considered, including test pattern generation software, hardware instrumentation, limit setting, IC design guidelines, and defect diagnosis. An extended reference list is provided to help the reader obtain more information on specific aspects.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00135333
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    Paper (German National Licenses)
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  • 2
    Electronic Resource
    Electronic Resource
    Reliability benefits of I DDQ (1992)
    Springer
    Journal of electronic testing 3 (1992), S. 327-335 
    Details
    ISSN: 1573-0727
    Keywords: I DDQ ; Gate oxide shorts ; reliability
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This is an application-oriented article on I DDQ to guide test engineers to a pragmatic method of implementing I DDQ . This article focuses on different aspects of I DDQ testing; quality, reliability, and test implementation. A description of I DDQ is presented, with different practical methods of implementing it, with empirical reliability data of I DDQ failures, and with empirical burn-in data identifying potential yield benefits. Employing I DDQ testing on digital CMOS technology, the user obtains a product with greater reliability. The data presented within this article, along with increasing customer focus on zero defects, clearly support I DDQ implementation.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00135336
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  • 3
    Electronic Resource
    Electronic Resource
    Diagnosis of leakage faults with I DDQ (1992)
    Springer
    Journal of electronic testing 3 (1992), S. 367-375 
    Details
    ISSN: 1573-0727
    Keywords: Fault diagnosis ; I DDQ testing ; leakage fault model
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Recently there has been renewed interest in fault detection in static CMOS circuits through I DDQ monitoring. This work shows that, in addition to fault detection, accurate fault diagnosis may be performed using a combination of current and voltage observations. The proposed system combines a simple single fault model for test generation with a more realistic multiple defect model for diagnosis, and as a result requires only minor modifications to existing stuck-at fault ATPG software. The associated hardware is sufficiently simple that on-board implementation is possible. Experimental results demonstrate the effectiveness of the method on a standard-cell ASIC.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00135340
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  • 4
    Electronic Resource
    Electronic Resource
    Quietest: A methodology for selecting I DDQ test vectors (1992)
    Springer
    Journal of electronic testing 3 (1992), S. 349-357 
    Details
    ISSN: 1573-0727
    Keywords: Leakage faults ; I DDQ testing ; weak faults
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Even high stuck-at fault coverage manufacturing test programs cannot assure high quality for CMOS VLSI circuits. Measurement of quiescent power supply current (I DDQ ) is a means of improving quality and reliability by detecting many defects that do not have appropriate representation in the stuck-at fault model. Since each I DDQ measurement takes significant time, a hierarchical fault analysis methodology is proposed for selecting a small subset of production test vectors for I DDQ measurements. A software system QUIETEST has been developed on the basis of this methodology. For two VLSI circuits QUIETEST selected less than 1% of production test vectors for covering all modeled faults that would have been covered by I DDQ measurement for all of the vectors. The fault models include leakage faults and weak faults for representing defects such as gate oxide shorts and certain opens.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00135338
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  • 5
    Electronic Resource
    Electronic Resource
    Algorithms for I DDQ measurement based diagnosis of bridging faults (1992)
    Springer
    Journal of electronic testing 3 (1992), S. 377-385 
    Details
    ISSN: 1573-0727
    Keywords: Bridging faults ; diagnosis algorithm ; I DDQ testing
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract In the absence of information about the layout one is left with no alternative but to consider all bridging faults. An algorithm for diagnosis of a subset of such faults, viz. single two line bridging faults in static CMOS combinational circuits is presented. This algorithm uses results from I DDQ measurement based testing. Unlike known diagnosis algorithms, this algorithm does not use fault dictionaries, it uses only logic simulation and uses no fault simulation. It also uses SOPS, a novel representation of subsets of two-line bridging faults resulting in an efficient algorithm. In spite of the large number of faults that we consider, our experimental results point to the computational feasibility of I DDQ Measurement based diagnosis of single two line bridging faults. It also shows the effectiveness of reducing the set of possible faults using I DDQ measurements.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00135341
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  • 6
    Electronic Resource
    Electronic Resource
    Generation and evaluation of current and logic tests for switch-level sequential circuits (1992)
    Springer
    Journal of electronic testing 3 (1992), S. 359-366 
    Details
    ISSN: 1573-0727
    Keywords: Current tests ; I DDQ ; logic tests ; test generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract This article presents an approach to developing high quality tests for switch-level circuits using both current and logic test generation algorithms. Faults that are aborted or undetectable by logic tests may be detected by current tests, or vice versa. An efficient switch level test generation algorithm for generating current and logic tests is introduced. Clear definitions for analyzing the effectiveness of the joint test generation approach are derived. Experimental results are presented for demonstrating high coverage of stuck-at, stuck-on, and stuck-open faults for switch level circuits when both current and logic tests are used.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00135339
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