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  • Articles  (3)
  • I DDQ testing  (3)
  • 1990-1994  (3)
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  • 1992  (3)
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  • Electrical Engineering, Measurement and Control Technology  (3)
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  • Articles  (3)
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  • 1990-1994  (3)
  • 1985-1989
  • 1960-1964
  • 1950-1954
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  • Electrical Engineering, Measurement and Control Technology  (3)
  • 1
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 3 (1992), S. 367-375 
    ISSN: 1573-0727
    Keywords: Fault diagnosis ; I DDQ testing ; leakage fault model
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Recently there has been renewed interest in fault detection in static CMOS circuits through I DDQ monitoring. This work shows that, in addition to fault detection, accurate fault diagnosis may be performed using a combination of current and voltage observations. The proposed system combines a simple single fault model for test generation with a more realistic multiple defect model for diagnosis, and as a result requires only minor modifications to existing stuck-at fault ATPG software. The associated hardware is sufficiently simple that on-board implementation is possible. Experimental results demonstrate the effectiveness of the method on a standard-cell ASIC.
    Type of Medium: Electronic Resource
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  • 2
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 3 (1992), S. 349-357 
    ISSN: 1573-0727
    Keywords: Leakage faults ; I DDQ testing ; weak faults
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Even high stuck-at fault coverage manufacturing test programs cannot assure high quality for CMOS VLSI circuits. Measurement of quiescent power supply current (I DDQ ) is a means of improving quality and reliability by detecting many defects that do not have appropriate representation in the stuck-at fault model. Since each I DDQ measurement takes significant time, a hierarchical fault analysis methodology is proposed for selecting a small subset of production test vectors for I DDQ measurements. A software system QUIETEST has been developed on the basis of this methodology. For two VLSI circuits QUIETEST selected less than 1% of production test vectors for covering all modeled faults that would have been covered by I DDQ measurement for all of the vectors. The fault models include leakage faults and weak faults for representing defects such as gate oxide shorts and certain opens.
    Type of Medium: Electronic Resource
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  • 3
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 3 (1992), S. 377-385 
    ISSN: 1573-0727
    Keywords: Bridging faults ; diagnosis algorithm ; I DDQ testing
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract In the absence of information about the layout one is left with no alternative but to consider all bridging faults. An algorithm for diagnosis of a subset of such faults, viz. single two line bridging faults in static CMOS combinational circuits is presented. This algorithm uses results from I DDQ measurement based testing. Unlike known diagnosis algorithms, this algorithm does not use fault dictionaries, it uses only logic simulation and uses no fault simulation. It also uses SOPS, a novel representation of subsets of two-line bridging faults resulting in an efficient algorithm. In spite of the large number of faults that we consider, our experimental results point to the computational feasibility of I DDQ Measurement based diagnosis of single two line bridging faults. It also shows the effectiveness of reducing the set of possible faults using I DDQ measurements.
    Type of Medium: Electronic Resource
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