ALBERT

Description: Sample preparation plays an essential role in most biochemical reactions. Raw reactants are diluted to solutions with desirable concentration values in this process. Since the reactants, like infant’s blood, DNA evidence collected from crime scenes, or costly reagents, are extremely valuable, their usage should be minimized whenever possible. In this paper, we propose a two-phased reactant minimization algorithm (REMIA), for sample preparation on digital microfluidic biochips. In the former phase, REMIA builds a reactant-minimized interpolated dilution tree with specific leaf nodes for a target concentration. Two approaches are developed for tree construction; one is based on integer linear programming (ILP) and the other is heuristic. The ILP one guarantees to produce an optimal dilution tree with minimal reactant consumption, whereas the heuristic one ensures runtime efficiency. Then, REMIA constructs a forest consisting of exponential dilution trees to produce those aforementioned specific leaf nodes with minimal reactant consumption in the latter phase. Experimental results show that REMIA achieves a reduction of reactant usage by 32%–52% as compared with three existing state-of-the-art sample preparation approaches. Besides, REMIA can be easily extended to solve the sample preparation problem with multiple target concentrations, and the extended version also effectively lowers the reactant consumption further.

Description: The 3-D integrated dynamic random-access memory (DRAM) structure with a processor is being widely studied due to advantages, such as a large band-width and data communication power reduction. In these structures, the massive heat generation of the processor results in a high operating temperature and a high refresh rate of the DRAM. Thus, in the 3-D DRAM over processor architecture, temperature-aware refresh management is necessary. However, temperature determination is difficult, because in the 3-D DRAM, the temperature changes dynamically and temperature variation in a DRAM die is complicated. In this paper, a thermal guard-band set-up method for 3-D stacked DRAM is proposed. It considers the latency of the temperature data and the position difference between the temperature sensor and the DRAM cell. With this method, the data reliability of the on-chip temperature sensor-dependent adaptive refresh control is guaranteed. In addition, an efficient temperature sensor built-in and refresh control method is analyzed. The expected refresh power reduction is examined through a simulation.

Description: Design of power delivery system has great influence on the power management in many-core processor systems. Moving voltage regulators from off-chip to on-chip gains more and more interest in the power delivery system design, because it is able to provide fine-grained dynamic voltage scaling. Previous works are proposed to implement power efficient on-chip voltage regulators. It is important to analyze the characteristics of the entire power delivery system to explore the tradeoff between the promising properties and costs of employing on-chip voltage regulators, especially the on-chip buck converters. In this paper, we present a novel analysis and design optimization platform of power delivery system called power supply on-chip (PowerSoC). It employs an analytical model to provide an accurate and fast evaluation of important characteristics, e.g., power efficiency, output stability, and dynamic voltage scaling, for the entire power delivery system consisting of on-chip/off-chip buck converters and power delivery network. Based on our model, geometric programming is utilized to find the optimal design for different power delivery systems and explore the tradeoff of using on-chip converters. Compared with SPICE simulations, our model achieves a simulation time reduction of six to seven orders of magnitude within 5% model error for the characteristic evaluation of different power delivery systems. By using PowerSoC, various architectures of power delivery systems are optimized for power efficiency under constraints of output stability, area, etc. Simulation results show that the hybrid architecture, consisting of both on-chip and off-chip converters, achieves 1.0% power efficiency improvement and 66.4% area reduction of converters, compared to the conventional design. We conclude the hybrid architecture has potential for efficient dynamic voltage scaling, small area, and the adaptability of the change of power delivery network parasitic, but ca- eful account for the overhead of on-chip converters is needed.

Description: As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, fabricated ICs become more susceptible to wear-outs, causing operation failure. Even a single link failure within an on-chip fabric can halt communication between application blocks, which makes the entire chip useless. In this paper, we aim to make faulty chips designed with network-on-chip (NoC) communication usable. Specifically, we present fault-tolerant irregular topology-generation method for application-specific NoC designs. Designed NoC topology allows different routing path if there is a link failure on the default routing path. Additionally, we present a simulated annealing-based application mapping algorithm aiming to minimize total energy consumption of the NoC design. We compare fault-tolerant topologies with nonfault-tolerant application-specific irregular topologies on energy consumption, performance, and area using multimedia benchmarks and custom-generated graphs. Our results demonstrate that our method is able to determine fault-tolerant topologies with negligible area increase and better energy values.

Description: Three-dimensional (3-D) integration is an attractive technology platform for next-generation ICs. Despite the benefits offered by 3-D integration, test cost remains a major concern, and analysis and tools are needed to understand test flows and minimize test cost. We propose a generic cost model to account for various test costs involved in 3-D integration and present a formal representation of the solution space to minimize the overall cost. We present an algorithm based on A*—a best-first search technique—to obtain an optimal solution. An approximation algorithm with provable bounds on optimality is proposed to further reduce the search space. In contrast to prior work, which is based on explicit enumeration of test flows, we adopt a formal optimization approach, which allows us to select an effective test flow by systematically exploring an exponentially large number of candidate test flows. Experimental results highlight the effectiveness of the proposed method. Adopting a formal approach to solving the cost-minimization problem provides useful insights that cannot be derived via selective enumeration of a smaller number of candidate test flows.

Description: The new era of cognitive computing brings forth the grand challenge of developing systems capable of processing massive amounts of noisy multisensory data. This type of intelligent computing poses a set of constraints, including real-time operation, low-power consumption and scalability, which require a radical departure from conventional system design. Brain-inspired architectures offer tremendous promise in this area. To this end, we developed TrueNorth, a 65 mW real-time neurosynaptic processor that implements a non-von Neumann, low-power, highly-parallel, scalable, and defect-tolerant architecture. With 4096 neurosynaptic cores, the TrueNorth chip contains 1 million digital neurons and 256 million synapses tightly interconnected by an event-driven routing infrastructure. The fully digital 5.4 billion transistor implementation leverages existing CMOS scaling trends, while ensuring one-to-one correspondence between hardware and software. With such aggressive design metrics and the TrueNorth architecture breaking path with prevailing architectures, it is clear that conventional computer-aided design (CAD) tools could not be used for the design. As a result, we developed a novel design methodology that includes mixed asynchronous–synchronous circuits and a complete tool flow for building an event-driven, low-power neurosynaptic chip. The TrueNorth chip is fully configurable in terms of connectivity and neural parameters to allow custom configurations for a wide range of cognitive and sensory perception applications. To reduce the system’s communication energy, we have adapted existing application-agnostic very large-scale integration CAD placement tools for mapping logical neural networks to the physical neurosynaptic core locations on the TrueNorth chips. With that, we have successfully demonstrated the use of TrueNorth-based systems in multiple applications, including visual object recognition, with higher performance and orders of magnitude lower- power consumption than the same algorithms run on von Neumann architectures. The TrueNorth chip and its tool flow serve as building blocks for future cognitive systems, and give designers an opportunity to develop novel brain-inspired architectures and systems based on the knowledge obtained from this paper.

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Description: Many commercial systems in the embedded space have shown weakness against power analysis-based side-channel attacks in recent years. Random masking is a commonly used technique for removing the statistical dependency between the sensitive data and the side-channel information. However, the process of designing masking countermeasures is both labor intensive and error prone. Furthermore, there is a lack of formal methods for quantifying the actual strength of a countermeasure implementation. Security design errors may therefore go undetected until the side-channel leakage is physically measured and evaluated. We show a better solution based on static analysis of C source code. We introduce the new notion of quantitative masking strength (QMS) to estimate the amount of information leakage from software through side channels. Once the user has identified the sensitive variables, the QMS can be automatically computed from the source code of a countermeasure implementation. Our experiments, based on measurement on real devices, show that the QMS accurately reflects the side-channel resistance of the software implementation.

Description: Currently available electronic design automation tools for design space exploration of solid state drives (SSDs) are not able to assess: 1) the device architecture inefficiencies; 2) architecture overdesign for a target performance; and 3) performance degradation caused by the disk usage. These tools feature either an overly high abstraction modeling strategy or lack the required flexibility to perform design exploration. To overcome these problems, this paper proposes SSDExplorer, a tool for fine-grained yet reasonably fast design space exploration of different SSD architectures highlighting possible bottlenecks. To prove its accuracy SSDExplorer has been validated with two real SSDs. SSDExplorer efficiency has been assessed by evaluating the impact of the NAND flash read retry algorithm impact on the SSD performance as a function of its internal architecture.

Description: Radiation-induced soft errors have become a key challenge in advanced commercial electronic components and systems. We present the results of a soft error rate (SER) analysis of an embedded processor. Our SER analysis platform accurately models generation, propagation, and masking effects starting from a technology response model derived using TCAD simulations at the device level all the way to application masking. The platform employs a combination of accurate models at the device level, analytical error propagation at gate level, and fault emulation at the architecture/application level to provide the detailed contribution of each component (flip-flops, combinational gates, and SRAMs) to the overall SER. At each stage in the modeling hierarchy, an appropriate level of abstraction is used to propagate the effect of errors to the next higher level. Unlike previous studies which are based on very simple test chips, analyzing the entire processor gives more insight into the relative contributions of combinational and sequential SER. The results of this analysis can assist circuit designers to adopt effective hardening techniques to reduce the overall SER while meeting the required power and performance constraints.

Description: To improve the efficiency of direct solution methods in SPICE-accurate integrated circuit (IC) simulations, preconditioned iterative solution techniques have been widely studied in the past decades. However, it is still an extremely challenging task to develop robust yet efficient general-purpose preconditioning methods that can deal with various types of large-scale IC problems. In this paper, based on recent graph sparsification research we propose circuit-oriented general-purpose support-circuit preconditioning (GPSCP) methods to dramatically improve the sparse matrix solution time and reduce the memory cost during SPICE-accurate IC simulations. By sparsifying the Laplacian matrix extracted from the original circuit network using graph sparsification techniques, general-purpose support circuits can be efficiently leveraged as preconditioners for solving large Jacobian matrices through Krylov-subspace iterations. Additionally, a performance model-guided graph sparsification framework is proposed to help automatically build nearly-optimal GPSCP solvers. Our experiment results for a variety of large-scale IC designs show that the proposed preconditioning techniques can achieve up to $18 {times }$ runtime speedups and $7 {times }$ memory reduction in DC and transient simulations when compared to state-of-the-art direct solution methods.

Description: Electron-beam (e-beam) lithography has long been employed for mask writing but the write time is increasing due to the escalating mask pattern complexity. Besides, e-beam direct write is being pursued as an alternative solution for chip production in the sub-22 nm regime. To improve the throughput of e-beam lithography, character projection method is commonly employed and a critical problem is to pack as many useful characters as possible onto the stencil. In this paper, we consider three enhancements in packed stencil design over previous works. First, the fact that the pattern of a character can be located anywhere within its enclosing projection region is exploited to facilitate flexible blank space sharing. Second, the use of multiple shaping apertures with different sizes is explored. Third, the use of overlapping shots for printing some characters is investigated. For the packed stencil design problem with flexible blank space sharing and multiple shaping apertures, two dynamic programming-based algorithms are proposed, one allows overlapping shots and the other does not. Experimental results show that the proposed enhancement and the associated algorithms can significantly reduce the total shot count and hence improve the throughput of e-beam lithography.

Description: This paper proposes an efficient algorithm that maximizes performance under power constraints and is applicable in the general context of traditional dynamic voltage/frequency (V/P) scaling, or core heterogeneity and emerging dynamic micro-architectural adaptation. Performance maximization in these scenarios can be essentially viewed as mapping application threads to appropriate core states that have various power/performance characteristics. Such problems are formulated as a generic 0-1 integer linear program (ILP). The proposed algorithm is an iterative heuristic-based solution. Compared with an optimal solution generated by commercial ILP solver, the proposed algorithm produces results less than 1% away from optimum on average, with more than two orders of magnitude improvement in runtime. The algorithm can be brought online for hundred-core heterogeneous systems as it scales to systems comprised of 256 cores with less than 1 ms in overhead in worst cases. The intrinsic history awareness also provides flexibility to control cost induced by switching V/F pairs, migrating threads across cores, or tuning on/off micro-architectural resources. 1 A villainous son of Poseidon in Greek mythology who forces travelers to fit into his bed by stretching their bodies or cutting off their legs (adapted from Merriam-Webster).

Description: Graphics processing units (GPUs) have become ubiquitous for general purpose applications due to their tremendous computing power. Initially, GPUs only employ scratchpad memory as on-chip memory. Though scratchpad memory benefits many applications, it is not ideal for those general purpose applications with irregular memory accesses. Hence, GPU vendors have introduced caches in conjunction with scratchpad memory in the recent generations of GPUs. The caches on GPUs are highly configurable. The programmer or compiler can explicitly control cache access or bypass for global load instructions. This highly configurable feature of GPU caches opens up the opportunities for optimizing the cache performance. In this paper, we propose an efficient compiler framework for cache bypassing on GPUs. Our objective is to efficiently utilize the configurable cache and improve the overall performance for general purpose GPU applications. In order to achieve this goal, we first characterize GPU cache utilization and develop performance metrics to estimate the cache reuses and memory traffic. Next, we present efficient algorithms that judiciously select global load instructions for cache access or bypass. Finally, we present techniques to explore the unified cache and shared memory design space. We integrate our techniques into an automatic compiler framework that leverages parallel thread execution instruction set architecture to enable cache bypassing for GPUs. Experiments evaluation on NVIDIA GTX680 using a variety of applications demonstrates that compared to cache-all and bypass-all solutions, our techniques improve the performance from 4.6% to 13.1% for 16 KB L1 cache.

Description: Nonvolatile memory (NVM) has many benefits compared to the traditional static RAM, such as improved reliability and reduced power consumption, but it has long write latency and limited write endurance. Scratchpad memory (SPM) is software-managed small on-chip memory for improving system performance and predicability. We consider SPM based on spin-transfer torque RAM, a type of NVM with high performance and good endurance. We present algorithms for allocating data variables to SPM and distribute write activity evenly in the SPM address space, in order to achieve wear-leveling and prolong the lifetime of NVM. We present two optimization algorithms for minimizing system CPU utilization subject to NVM lifetime constraints: 1) an optimal algorithm based on ILP and 2) an efficient heuristic algorithm that can obtain close-to-optimal solutions.

Description: Finite field arithmetic operations have been traditionally used in different applications ranging from error control coding to cryptographic computations. Among these computations are normal basis multiplications and exponentiations which are utilized in efficient applications due to their advantageous characteristics and the fact that squaring (and subsequent powering by two) of elements can be obtained with no hardware complexity. In this paper, we present 2-D decomposition systolic-oriented algorithms to develop systolic structures for digit-level Gaussian normal basis multiplication and exponentiation over $ {GF}({2}^{m})$ . The proposed high-performance architectures are suitable for a number of applications, e.g., architectures for elliptic curve Diffie–Hellman key agreement scheme in cryptography. The results of the benchmark of efficiency, performance, and implementation metrics of such architectures through a 65-nm application-specific integrated circuit platform confirm high-performance structures for the multiplication and exponentiation architectures presented in this paper are suitable for high-speed architectures, including cryptographic applications.

Description: This paper introduces a new methodology for pipeline synthesis with applications to data flow high-level system design. The pipeline synthesis is applied to dataflow programs whose operators are translated into graphs and dependencies relations that are then processed for the pipeline architecture optimization. For each pipeline-stage time, a minimal number of pipeline stages are first determined and then an optimal assignment of operators to stages is generated with the objective of minimizing the total pipeline register size. The obtained “optimal” pipeline schedule is automatically transformed back into a dataflow program that can be synthesized to efficient hardware implementations. Two new pipeline scheduling: “least cost search branch and bound” and a heuristic technique have been developed. The first algorithm yields global optimum solutions for middle size designs, whereas the second one generates close-to-optimal solutions for large designs. Experimental results on FPGA designs show that the total pipeline register size gain in a range up to $4.68 {times } $ can be achieved. The new algorithms overcome the known downward and upward direction dataflow graph traversal algorithms concerning the amount of pipeline register size by up to 100% on average.

Description: In analog designs, the most widely adopted layout practice to improve matching is the symmetrical common-centroid placement. However, this arrangement cannot be obtained in general. In this paper, it is shown that there are asymmetrical placements with a common centroid which are also immune to process gradients and suitable for designs where a symmetrical layout is not possible. In addition, this paper proposes an automated method, based on a standard simulated annealing framework, to arrange fully-integrated capacitors in a layout to improve their matching.

Description: With the steady growth of chip complexity and shrinking feature size, multiple challenges are emerging for transistor level circuit simulation. Compact SPICE models are a fundamental part of circuit verification, serving as a bridge between the semiconductor design and foundry. It is also an integral part of SPICE simulators, which directly affects tool performance and therefore design schedule. While the advanced 3-D technology nodes deliver superior level of scalability, simulation cost is rapidly increasing due to the computational complexity introduced by device model equations and the number of iterations required for numerical methods. In this paper, an efficient solution is proposed to reduce the computational cost associated with UC Berkeley BSIM-CMG device model evaluation, by applying robust Verilog compiler and computer algebra techniques to the device model equations. As a result of this implementation, simulation time reduction is up to 72% for complex blocks of the latest generation processor design.

Description: The hardware Trojan threat has motivated development of Trojan detection schemes at all stages of the integrated circuit (IC) lifecycle. While the majority of existing schemes focus on ICs at test-time, there are many unique advantages offered by post-deployment/run-time Trojan detection. However, run-time approaches have been underutilized with prior work highlighting the challenges of implementing them with limited hardware resources. In this paper, we propose three innovative low-overhead approaches for run-time Trojan detection which exploit the thermal sensors already available in many modern systems to detect deviations in power/thermal profiles caused by Trojan activation. The first one is a local sensor-based approach that uses information from thermal sensors together with hypothesis testing to make a decision. The second one is a global approach that exploits correlation between sensors and maintains track of the ICs thermal profile using a Kalman filter (KF). The third approach incorporates leakage power into the system dynamic model and apply extended KF (EKF) to track ICs thermal profile. Simulation results using state-of-the-art tools on ten publicly available Trojan benchmarks verify that all three proposed approaches can detect active Trojans quickly and with few false positives. Among three approaches, EKF is flawless in terms of the ten benchmarks tested but would require the most overhead.

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Description: As nanometer technology advances, conventional optical proximity correction (OPC) that minimizes the edge placement error (EPE) at the nominal process condition alone often leads to poor process windows. To improve the mask printability across various process corners, process-window OPC optimizes EPE for multiple process corners, but often suffers long runtime, due to repeated lithographic simulations. This paper presents an efficient process variation (PV)-aware mask optimization framework, namely PVOPC, to simultaneously minimize EPE and PV band with fast convergence. The PVOPC framework includes EPE-sensitivity-driven dynamic fragmentation, PV-aware EPE modeling, and correction with three new EPE-converging techniques and a systematic subresolution-assisted feature insertion algorithm. Experimental results show that our approach efficiently achieves high-quality EPE and PV band results.

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Description: Binning after volume production is a widely accepted technique to classify fabricated integrated circuits (ICs) into different clusters depending on different degrees of specification compliance. This allows the manufacturer to sell nonoptimal devices at lower rates, so adapting to customer’s quality-price requirements. The binning procedure can be carried out by measuring every single circuit performances, but this approach is costly and time-consuming. On the contrary, if alternate measurements are used to characterize the bins, the procedure is considerably enhanced. In such a case, the specification bin boundaries become arbitrary shape regions due to the highly nonlinear mappings between the specifications space and the alternate measurements space. The binning strategy proposed in this paper functions with the same efficiency regardless of these shapes. The digital encoding of the bins in the alternate measurements space using octrees is the key idea of the proposal. The strategy has two phases: 1) the training phase and 2) the binning phase. In the training phase, the specification bins are encoded using octrees. This first phase requires sufficient samples of each class to generate the octree under realistic variations, but it only needs to be performed once. The binning phase corresponds to the actual production binning of the fabricated ICs. This is achieved by evaluating the alternate measurements in the previously generated octree. The binning phase is fast due to the inherent sparsity of the octree data structure. In order to illustrate the proposal, the method has been applied to a band-pass Butterworth filter considering three specification bins as a proof of concept. Successful simulation results are reported showing considerable advantages as compared to a support vector machine (SVM)-based classifier. Similar bin misclassifications are obtained with both methods, 1.68% using octrees and 1.83% using SVM, while binning time is $5times $ times faster using octrees than using the SVM-based classifier.

Description: With shrinking process technology, decreasing supply voltage, and increasing clock frequency, noise reduction becomes more and more crucial to the success of modern mixed-signal system-on-chip design. To eliminate the switching noise due to crosstalk coupling between analog and digital signals, it is essential to fully separate the routing paths of analog and digital nets when generating mixed-signal layouts. Different from previous works which cannot fully separate analog and digital routing paths, this paper presents a novel hierarchical deterministic mixed-signal layout synthesis approach with the separation of analog and digital signal paths for switching noise elimination. Experimental results based on a third-order $ {Sigma Delta }$ modulator show that the proposed approach can result in various layouts with separated analog and digital signal paths while achieving better signal-to-noise and distortion ratio, and overall performance specifications.

Description: Efficient performance modeling of today’s analog and mixed-signal circuits is an important yet challenging task, due to the high-dimensional variation space and expensive circuit simulation. In this paper, we propose a novel performance modeling algorithm that is referred to as Bayesian model fusion (BMF) to address this challenge. The key idea of BMF is to borrow the information collected from an early stage (e.g., schematic level) to facilitate efficient performance modeling at a late stage (e.g., post layout). Such a goal is achieved by statistically modeling the performance correlation between early and late stages through Bayesian inference. Furthermore, to make the proposed BMF method of practical utility, four implementation issues, including: 1) prior mapping; 2) missing prior knowledge; 3) fast solver; and 4) prior and hyper-parameter selection, are carefully considered in this paper. Two circuit examples designed in a commercial 32 nm CMOS silicon on insulator process demonstrate that the proposed BMF method achieves up to $9times $ runtime speed-up over the traditional modeling technique without surrendering any accuracy.

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Description: Layout-dependent effects (LDEs) have become a critical issue in modern analog and mixed-signal circuit designs. The three major sources of LDEs, well proximity, length of oxide diffusion, and oxide-to-oxide spacing, significantly affect the threshold voltage and mobility of devices in advanced technology nodes. In this paper, we propose the first work to consider the three major sources of LDEs during analog placement. We first transform the three LDE models into nonlinear analytical placement models. Then an LDE-aware analytical analog placement algorithm is presented to mitigate the influence of the LDEs while improving circuit performance. Experimental results show that our placement algorithm can effectively and efficiently reduce the LDE-induced variations and improve circuit performance.

Description: Reconfigurable digital filter is being widely used in applications such as communication and signal processing. Its performance, power consumption, and logic resource utilization are the major factors to be taken into consideration when designing the filters. This paper proposes a concise canonic signed digit coefficient grouping method aiming at reducing the number of common subexpressions (CSs). Further, we statistically analyze every CS occurance for numerous sorts of the finite-impulse response (FIR) filters and obtain characterization of the distribution behavior for all the possible CS patterns in a 16-bit coefficient. Thus, a novel processing element structure is proposed to form a medium-grain array for computationally efficient realization of reconfigurable FIR filter. The experiment results suggest such design implementations typically achieve 21% reduction in silicon area, 20% decrease in power consumption, and 14% improvement in operation speed in comparison to other conventional FIR architectures.

Description: Digital microfluidic biochips (DMFBs) are gaining increasing attention with promising applications for automating and miniaturizing laboratory procedures in biochemistry. In DMFBs, cross-contamination of droplets with different biomolecules is a major issue, which causes significant errors in bioassays. Washing operations are introduced to clean the cross-contamination spots. However, existing works have oversimplified assumptions on the washing behavior, which either assume infinite washing capacity, or ignore the routing conflicts between functional and washing droplets. This paper proposes the first integrated functional and washing droplet routing flow, which considers practical issues including the finite washing capacity constraint, and the routing conflicts between functional and washing droplets. Washing droplets of different sizes are also proposed to wash the congested cross-contamination spots. Effectiveness of the proposed method is validated by real-life biochemical applications.

Description: It is known that bus-oriented escape routing and area routing are necessary in a high-speed printed circuit board (PCB) design. In this paper, given a set of global routed buses in a high-speed PCB design, it is assumed that the routed nets in a single bus are represented as a bus-oriented net between two escaped boundary pins. Based on the construction of a virtual wall between two circuit components, the connection transformation of the given bus-oriented nets inside a closed region and the construction of a covering graph for the represented intervals, an iterative modified left-edge algorithm is proposed to minimize the number of the assigned layers and assign all the bus-oriented nets onto the available layers. Compared with Tsai’s algorithm, the experimental results show that our proposed algorithm reduces 15.0% of the layer number and 21.9% of CPU time for six tested examples on the average, respectively. Compared with Chin’s algorithm, the experimental results show that our proposed algorithm use less CPU time to reduce 15.0% of the layer number for six tested examples on the average.

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Description: Applications executed on multicore embedded systems interact with system software [such as the operating system (OS)] and hardware, leading to widely varying thermal profiles which accelerate some aging mechanisms, reducing the lifetime reliability. Effectively managing the temperature therefore requires: 1) autonomous detection of changes in application workload and 2) appropriate selection of control levers to manage thermal profiles of these workloads. In this paper, we propose a technique for workload change detection using density ratio-based statistical divergence between overlapping sliding windows of CPU performance statistics. This is integrated in a runtime approach for thermal management, which uses reinforcement learning to select workload-specific thermal control levers by sampling on-board thermal sensors. Identified control levers override the OSs native thread allocation decision and scale hardware voltage–frequency to improve average temperature, peak temperature, and thermal cycling. The proposed approach is validated through its implementation as a hierarchical runtime manager for Linux, with heuristic-based thread affinity selected from the upper hierarchy to reduce thermal cycling and learning-based voltage–frequency selected from the lower hierarchy to reduce average and peak temperatures. Experiments conducted with mobile, embedded, and high performance applications on ARM-based embedded systems demonstrate that the proposed approach increases workload change detection accuracy by an average ${3.4times }$ , reducing the average temperature by 4 °C–25 °C, peak temperature by 6 °C–24 °C, and thermal cycling by 7%–35% over state-of-the-art approaches.

Description: Near-threshold computing has emerged as a promising solution to significantly increase the energy efficiency of next-generation multicore systems. This paper evaluates and analyzes the behavior of dynamic voltage and frequency scaling for multicore systems operating under extended range: including near-threshold, nominal, and turbo modes. We adapt the model selection technique from machine learning to determine the relationship between performance and power. The theoretical results show that the resulting models satisfy convexity, which efficiently determines the optimal voltage/frequency operating points for: 1) minimizing energy consumption under throughput constraints or 2) maximizing throughput under a given power budget. We validate our models on FinFET-based chip-multiprocessors. Considering process variations (PVs), experimental results show that at 30% PV levels, our proposed method: 1) reduces energy consumption by 31.09% at iso-performance condition and 2) increases throughput by 11.46% at iso-power when compared with variation-agnostic nominal case.

Description: With the continuous scaling of CMOS devices, the increase in power density and system integration level have not only resulted in huge energy consumption but also led to elevated chip temperature. Thus, energy efficient task scheduling with thermal consideration has become a pressing research issue in computing systems, especially for real-time embedded systems with limited cooling techniques. In this paper, we design a two-stage energy-efficient temperature-aware task scheduling scheme for heterogeneous real-time multiprocessor system-on-chip (MPSoC) systems. In the first stage, we analyze the energy optimality of assigning real-time tasks to multiple processors of an MPSoC system, and design a task assignment heuristic that minimizes the system dynamic energy consumption under the constraint of task deadlines. In the second stage, the optimality of minimizing the peak temperature of a processor is investigated, and a slack distribution heuristic is proposed to improve the temperature profile of each processor under the thermal constraint, thus the temperature-dependent system leakage energy consumption is reduced. Through the extensive efforts made in two stages, the system overall energy consumption is minimized. Experimental results have demonstrated the effectiveness of our scheme.

Description: A black-box method for modeling the time-domain response of integrated circuits (ICs) based on echo state networks is proposed. The number and value of the input and feedback delays required for modeling nonlinear systems with memory are detected automatically, and the training procedure is very fast and robust. The resulting models can be implemented in any hardware description language. The proposed modeling approach is applied to three test cases that cover a wide range of analog behavior. The achieved accuracy is comparable to the reference modeling method, and, depending on the complexity of the modeled IC, the simulation speed-up factor is in the order between 10 and 100.

Description: To guarantee high reliability, solid-state drive (SSD)-based storage systems require data redundancy schemes, e.g., redundant array of independent disks (RAID) schemes. Traditional RAID-5, RAID-6, and Reed-Solomon codes can tolerate one, two, and an arbitrary number of device failures, respectively. However, some SSDs under those redundant configurations may age much faster than others because of the high skewness and locality of workloads. The uneven aging rates may make some SSDs wear out very quickly and decrease the endurance of SSD-based RAID arrays. To address this problem, we first come up with a diagonal coding scheme (DCS) by distributing the updating dependencies evenly among devices to improve the system-level wear-leveling. DCS can efficiently improve the array endurance if requests are aligned with the stripe size, i.e., when data symbols in the same stripe receive the same number of writes, while the number could be different for different stripes. To relax the above assumption, we further propose an enhanced scheme, DCS+. With a buffer design, DCS+ can improve the wear-leveling among devices under general access patterns via triggering different responses to different kinds of requests. We conduct extensive trace-driven evaluations based on real-world workloads, and results show that our design efficiently enhances the endurance of SSD-based RAID arrays.

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Description: Self-aligned double patterning (SADP) is being considered for use at the 10-nm technology node and below for routing layers with pitches down to ~50 nm because it has better line edge roughness and overlay control compared to other multiple patterning candidates. To date, most of the SADP-related literature has focused on enabling SADP-legal routing in physical design tools while few attempts have been made to address the impact SADP routing has on local, standard cell (SC) I/O pin access. At the same time, via layers are used to connect the local SADP routing layers to the I/O pins on lower metal layers. Due to the high via density on the Via-1 layer, the litho-etch-litho-etch (LELE)-aware Via-1 design becomes a necessity to achieve legal pin access at the SC level. In this paper, we present the first study on SADP-aware pin access and layout optimization at the SC level. Accounting for SADP-specific and Via-1 design rules, we propose a coherent framework that uses depth first search, mixed integer linear programming, and backtracking method to enable LELE friendly Via-1 design and simultaneously optimize SADP-based local pin access and within-cell connections. Our experimental results show that, compared with the conventional approach, our framework effectively improves pin access of the SCs and maximizes the pin access flexibility for routing.

Description: We propose an electrostatics-based placement algorithm for large-scale mixed-size circuits (ePlace-MS). ePlace-MS is generalized, flat, analytic and nonlinear. The density modeling method eDensity is extended to handle the mixed-size placement. We conduct detailed analysis on the correctness of the gradient formulation and the numerical solution, as well as the rationale of dc removal and the advantages over prior density functions. Nesterov's method is used as the nonlinear solver, which shows high yet stable performance over mixed-size circuits. The steplength is set as the inverse of Lipschitz constant of the gradient function, while we develop a backtracking method to prevent overestimation. An approximated nonlinear preconditioner is developed to minimize the topological and physical differences between large macros and standard cells. Besides, we devise a simulated annealer to legalize the layout of macros and use a second-phase global placement to reoptimize the standard cell layout. All the above innovations are integrated into our mixed-size placement prototype ePlace-MS, which outperforms all the related works in literature with better quality and efficiency. Compared to the leading-edge mixed-size placer NTUplace3, ePlace-MS produces up to 22.98% and on average 8.22% shorter wirelength over all the 16 modern mixed-size benchmark circuits with the same runtime.

Description: Although self-aligned double and quadruple patterning (SADP, SAQP) have promising processes for sub-20 nm node advanced technologies and beyond, not all layouts are compatible with them. In advanced technologies, feasible wafer image should be generated effectively by utilizing SADP and SAQP where a wafer image is determined by a selected mandrel pattern. However, predicting a mandrel pattern is not easy since it is different from the wafer image (or target pattern). In this paper, we propose new routing methods for spacer-is-dielectric (SID)-type SADP, SID-type SAQP, and spacer-is-metal (SIM)-type SADP to generate a feasible layout satisfying the connection requirements. Routing algorithms comprising simple connecting and cutting rules are performed on a new grid structure where two (SID-type SADP) or three colors (SID-type SAQP and SIM-type SADP) are assigned alternately to grid-nodes. Then a mandrel pattern is selected without complex coloring or decomposition methods. Also, we try to reduce hotspots (potentially defective regions) by the proposed dummy pattern flipping for SID-type SADP. In experiments, feasible layouts meeting the connection requirements are generated and the effectiveness of the proposed framework is confirmed.

Description: As advances in manufacture technology, leakage current increases dramatically in modern ICs. By turning off supply voltage in a low-power domain with power switches, power gating becomes a useful technique in resolving this problem. Since number and locations of power switches have great impact on chip area and IR-drop, an efficient and effective approach to insert power switches is required for the power gating designs. Unlike previous works using the greedy algorithm to handle this problem, this paper uses a simplified model to approximate required equivalent resistance of power switches in a low-power domain, and then determines number and types of power switches based on the value. In order to reduce impact on preplaced standard cells, we also propose a mathematical approach to find locations with less placement density to place power switches. The proposed methodology was integrated into a real-design flow. Experimental results demonstrate that our approach can insert less number of power switches and still satisfy the IR-drop constraint than other approaches.

Description: In this paper, we study row-based detailed placement refinement for triple patterning lithography (TPL), which asks to find a refined detailed placement solution as well as a valid TPL layout decomposition under the objective of minimizing the number of stitches and the half-perimeter wirelength. Our problem does not have precoloring solutions of cells as the input, and it allows using techniques, including white space insertion, cell flipping, adjacent-cell swapping, and vertical cell movement, to optimize the solution quality. We first present (resource-constrained) shortest-path-based algorithms for several TPL-aware single-row placement problems that allow or disallow perturbing a given cell ordering. Based on these algorithms, we then propose an approach to our TPL-aware detailed placement refinement problem, which first minimizes the number of stitches and then minimizes the wirelength. Finally, we report extensive experimental results to demonstrate the effectiveness and efficiency of our approach.

Description: Memristors are an attractive option for use in future memory architectures but are prone to high defect densities due to the nondeterministic nature of nanoscale fabrication. Several works discuss memristor fault models and testing. However, none of them considers the memristor as a multilevel cell (MLC). The ability of memristors to function as an MLC allows for extremely dense, low-power memories. Using a memristor as an MLC introduces fault mechanisms that cannot occur in typical two-level memory cells. In this paper, we develop fault models for memristor-based MLC crossbars. The typical approach to testing a memory subsystem entails testing one memory cell at a time. However, this testing strategy is time consuming and does not scale for dense, memristor memories. We propose an efficient testing technique that exploits sneak-paths inherent in crossbar memories to test several memory cells simultaneously. In this paper, we integrate solutions for detecting and locating faults in memristors. We develop a power aware built-in self-test solution to detect these faults. We also propose a hybrid diagnosis scheme that uses a combination of sneak-path and March testing to reduce diagnosis time. The proposed schemes enable and leverage sneak-paths during fault detection and diagnosis modes, while disabling sneak-paths during normal operation. The proposed hybrid scheme reduces fault detection and diagnosis time by 24.69% and 28%, respectively, compared to traditional March tests.

Description: A multilayer routing system usually adopts multiple interconnect configuration with different wire sizes and thicknesses. Since thicker layers of metal lead to fatter wires with smaller resistance, the layer assignment (LA) of nets has a large impact on the interconnect delay. However, such layer-dependent characteristics have been ignored by most of the state-of-the-art academic LA methods. These characteristics also weaken the previous wire length-based antenna avoidance method, because the net length itself cannot accurately capture the antenna area under the condition of various wire sizes. To remedy this deficiency, this paper proposes a more effective three-stage LA algorithm under multitier interconnect structure, and focuses on minimizing delays, via count, and antenna violations. It first minimizes the total delay and via count simultaneously by dynamic programming and negotiation technique, and then further minimizes the maximum delay carefully while almost unchanging the via count. After that, a check-and-repair method is adopted to further fix the antenna violations. The experimental results on the International Conference on Computer-Aided Design'09 benchmarks show that the proposed algorithm can significantly reduce the total delay and maximum delay while still keeping roughly the same via count compared with the state-of-the-art via count minimization LA method negotiation-based via minimization algorithm. At the same time, the antenna violation repair method can dramatically reduce the antenna violated nets and sinks with little impact on the solution quality.

Description: As the feature size of semiconductor process further scales to sub-16 nm technology node, triple patterning lithography (TPL) has been regarded as one of the most promising lithography candidates along with extreme ultraviolet, electron beam lithography, and directly self-assembly. M1 and contact layers, which are usually deployed within standard cells, are the most critical and complex parts for modern digital designs. Traditional design flow that ignores TPL in early stages may limit the potential to resolve all the TPL conflicts. In this paper, we propose a coherent framework, including standard cell compliance and detailed placement, to enable TPL friendly design. Considering TPL constraints during early design stages, such as standard cell compliance, improves the layout decomposability. With the precoloring solutions of standard cells, we present a TPL aware detailed placement where the layout decomposition and placement can be resolved simultaneously. In addition, we propose a linear dynamic programming to solve TPL aware detailed placement with maximum displacement, which can achieve good trade-off in terms of runtime and performance. Experimental results show that our framework can achieve zero conflict, meanwhile can effectively optimize the stitch number and placement wire-length.

Description: Finite state machines with input multiplexing (FSMIMs) have been proposed in previous works as a technique for efficient mapping FSMs into ROM memory. In this paper, we propose a new architecture for implementing FSMIMs, called FSMIM with state-based input selection, whose goal is to achieve a further reduction in memory usage. This paper also describes in detail the algorithms for generating FSMIMs used by the tool FSMIM-Gen, which has been developed and made available on the Internet for free public use. A comparative study in terms of speed and area between FSMIM approaches and other field programmable gate array-based techniques is presented. The results show that the FSMIM approaches obtain huge reductions in the look-up table (LUT) usage by using a small number of embedded memory blocks. In addition, speed improvements over conventional LUT-based implementations have been obtained in many cases.

Description: Functional diagnosis for complex systems can be a very time-consuming and expensive task, trying to identify the source of an observed misbehavior. We propose an automatic incremental diagnostic methodology and CAD flow, based on data mining (DM). It is a model-based approach that incrementally determines the tests to be executed to isolate the faulty component, aiming at minimizing the total number of executed tests, without compromising 100% diagnostic accuracy. The DM engine allows for shorter test sequences with respect to other reasoning-based solutions (e.g., Bayesian belief networks), not requiring complex pre and post-conditions management. Experimental results on a large set of synthetic examples and on three industrial boards substantiate the quality of the proposed approach.

Description: A sub-threshold design could provide a compelling approach to power critical applications. An exponential relationship exists, however, between the delay and the threshold voltage, that makes this design-time timing closure extremely difficult, if not impossible, to achieve. Several previous studies were focused on the technique of body biasing during post-silicon tuning for delay compensation. But they were mostly for super-threshold designs where spatially correlated ${L} _{mathbf {eff}}$ variation dominates. They cannot be applied directly to sub-threshold designs in which purely random threshold voltage variations dominate. These works also assumed multiple body biasing voltage domains and multiple body biasing voltage levels, which involve significant design overhead. The problem of selective body biasing for post-silicon tuning of sub-threshold designs is examined in this paper. The possibility of using only one body bias voltage domain with a single body bias voltage is explored. The problem was formulated first as a linearly constrained statistical optimization model. The adaptive filtering concept from the signal processing community was then adopted so that an efficient, yet novel, solution could be developed. Using several 65 nm industrial designs, experimental results suggest that, compared with a seemingly more intuitive approach, the proposed approach can improve the pass rate by 57% on average with similar standby power and the same number of body biasing gates. This approach can reduce the standby power, on average, by 84%, with a 20% pass rate loss, more than the approach to bias all the gates.

Description: Scan design is a de facto design-for-testability (DfT) technique that enhances access during manufacturing test process. However, it can also be used as a back door to leak secret information from a secure chip. In existing scan attacks, the secret key of a secure chip is retrieved by using both the functional mode and the test mode of the chip. These attacks can be thwarted by applying a reset operation when there is a switch of mode. However, the mode-reset countermeasure can be thwarted by using only the test mode of a secure chip. In this paper, we perform a detailed analysis on the test-mode-only scan attack. We propose attacks on an advanced encryption standard (AES) design with a basic scan architecture as well as on an AES design with an advanced DfT infrastructure that comprises decompressors and compactors. The attack results show that indeed the secure chips are vulnerable to test-mode-only attacks. The secret key can be recovered within 1 s even in the presence of decompressors and compactors. We then propose new countermeasures to thwart these attacks. The proposed countermeasures incur minimal cost while providing high success rate.

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Description: Enterprise servers require customized solid-state drives (SSDs) to satisfy their specialized I/O performance and reliability requirements. For effective use of SSDs for enterprise purposes, SSDs must be designed considering requirements such as those related to performance, lifetime, and cost constraints. However, SSDs have numerous hardware and software design options, such as flash memory types and block allocation methods, which have not been well analyzed yet, but on which the SSD performance depends. Furthermore, there is no methodology for determining the optimal design for a particular I/O workload. This paper proposes SSD-Tailor, a customization tool for SSDs. SSD-Tailor determines a near-optimal set of design options for a given workload. SSD designers can use SSD-Tailor to customize SSDs in the early design stage to meet the customer requirements. We evaluate SSD-Tailor with nine I/O workload traces collected from real-world enterprise servers. We observe that SSD-Tailor finds near-optimal SSD designs for these workloads by exploring only about 1% of the entire set of design candidates. We also show that the near-optimal designs increase the average I/O operations per second by up to 17% and decrease the average response time by up to 163% as compared to an SSD with a general design.

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Description: Defects or traps in semiconductors and nano devices that randomly capture and emit charge carriers result in low-frequency noise, such as burst and 1/f noise, which are important concerns in the design of both analog and digital circuits. The capture and emission rates of these traps are functions of the time-varying voltages across the device, resulting in nonstationary noise characteristics. Modeling of low-frequency, nonstationary noise in circuit simulators is a long-standing open problem. It has been realized that the low-frequency noise models in circuit simulators were the culprits that produced erroneous noise performance results for circuits under strongly time-varying bias conditions. In this paper, we present two fully nonstationary models for traps, a fine-grained Markov chain model and a coarse-grained Langevin model based on similar models for ion channels in neurons. The nonstationary trap models we present subsume and unify all of the work that has been done recently in the device modeling and circuit design literature on modeling nonstationary trap noise. We provide a detailed explication of these models with regard to their stochastic properties and develop carefully crafted circuit simulation techniques that are stochastically correct. We have implemented the proposed techniques in a MATLAB-based circuit simulator, by expanding the industry standard compact MOSFET model PSP to include a nonstationary description of oxide traps. We present results obtained by this extended model and the proposed simulation techniques for the low-frequency noise characterization of a common source amplifier and the phase jitter of a ring oscillator.

Description: 3-D die-stacks hold great promise for increasing system performance, but difficulties in testing dies and assembling a 3-D stack are leading to yield issues and slowing the large scale manufacturing of these devices. In many cases, a single defective die will kill the entire stack. To help mitigate this issue, we explore the possibility of repairing a stack that contains a defective die by utilizing an field programmable gate array (FPGA) that has already been included in the stack for other purposes, such as performance enhancement. Specifically, we propose bypassing the defective portion of a nonprogrammable die by replacing the defective functionality with functionality on the FPGA. In this paper, we discuss what additional logic must be added to an Application-Specific Integrated Circuit (ASIC) die to allow such a bypass to occur. We then show through detailed simulation of a 2.5-D Xilinx FPGA how bypassing of logic can be achieved and throughput maintained even when the two different dies involved operate at different frequencies. Finally, we explore the performance of this technique in a superscalar, out-of-order processor, where different functional units are marked for replacement. Our simulation results show that not only can we salvage a device that would otherwise have to be discarded, but creating multiple copies of the defective partition in the FPGA can allow us to regain performance even when the latency of the units in the FPGA is longer than that of the original defective copy.

Description: Model order reduction of nonlinear circuits (especially highly nonlinear circuits) has always been a theoretically and numerically challenging task. In this paper, we utilize tensors (namely, a higher order generalization of matrices) to develop a tensor-based nonlinear model order reduction algorithm we named TNMOR for the efficient simulation of nonlinear circuits. Unlike existing nonlinear model order reduction methods, in TNMOR high-order nonlinearities are captured using tensors, followed by decomposition and reduction to a compact tensor-based reduced-order model. Therefore, TNMOR completely avoids the dense reduced-order system matrices, which in turn allows faster simulation and a smaller memory requirement if relatively low-rank approximations of these tensors exist. Numerical experiments on transient and periodic steady-state analyses confirm the superior accuracy and efficiency of TNMOR, particularly in highly nonlinear scenarios.

Description: The emerging trend toward utilizing chip multicore processors (CMPs) that support dynamic voltage and frequency scaling (DVFS) is driven by user requirements for high performance and low power. To overcome limitations of the conventional chip-wide DVFS and achieve the maximum possible energy saving, per-core DVFS is being enabled in the recent CMP offerings. While power consumed by the CMP is reduced by per-core DVFS, power dissipated by the set of voltage regulators (VRs) that are required to support per-core DVFS becomes critical. This paper focuses on the dynamic control of the VRs in a CMP platform. Starting with a proposed platform with a reconfigurable VR-to-core power distribution network (PDN), two optimization methods are presented to maximize the system-wide energy savings: 1) reactive VR consolidation (VRCon) to reconfigure the network for maximizing the power conversion efficiency of the VRs, which is performed under the predetermined DVFS levels for the cores and 2) proactive VRCon to determine new DVFS levels for maximizing the total energy savings without any performance degradation. Along with the optimization methods for the PDN composed of homogeneous VRs, we also discuss the PDN with heterogeneous VRs, which is proposed to increase the benefits of the VRCon by incorporating VRs with a larger driving capability of load current. Results from detailed simulations based on realistic experimental setups demonstrate up to 36% VR energy loss reduction and 9% total energy saving.

Description: Test compaction can be achieved by using multicycle tests. To avoid the computationally intensive process of sequential test generation, multicycle tests can be generated by extending two-cycle tests. However, the scan-in state of a two-cycle test is not always effective for a multicycle test when the primary input vectors are held constant during the functional clock cycles of a test. This paper studies the extent of this issue by considering exhaustive two-cycle and multicycle test sets with constant primary input vectors for finite-state machine benchmarks. Based on the results of this study, it describes an efficient test compaction procedure that modifies selected two-cycle tests in a given test set in order to make them more effective as a source for multicycle tests with constant primary input vectors. Experimental results are presented to demonstrate the importance of this step to test compaction.

Description: Carbon nanotube field-effect transistors (CNFETs) are promising candidates for building energy-efficient digital systems at highly scaled technology nodes. However, carbon nanotubes (CNTs) are inherently subject to variations that reduce circuit yield, increase susceptibility to noise, and severely degrade their anticipated energy and speed benefits. Joint exploration and optimization of CNT processing options and CNFET circuit design are required to overcome this outstanding challenge. Unfortunately, existing approaches for such exploration and optimization are computationally expensive, and mostly rely on trial-and-error-based ad hoc techniques. In this paper, we present a framework that quickly evaluates the impact of CNT variations on circuit delay and noise margin, and systematically explores the large space of CNT processing options to derive optimized CNT processing and CNFET circuit design guidelines. We demonstrate that our framework: 1) runs over $100boldsymbol {times }$ faster than existing approaches and 2) accurately identifies the most important CNT processing parameters, together with CNFET circuit design parameters (e.g., for CNFET sizing and standard cell layouts), to minimize the impact of CNT variations on CNFET circuit speed with ≤5% energy cost, while simultaneously meeting circuit-level noise margin and yield constraints.

Description: Embedded cryptographic devices are vulnerable to power analysis attacks. Threshold implementations (TIs) provide provable security against first-order power analysis attacks for hardware and software implementations. Like masking, the approach relies on secret sharing but it differs in the implementation of logic functions. While masking can fail to provide protection due to glitches in the circuit, TIs rely on few assumptions about the hardware and are fully compatible with standard design flows. We investigate two important properties of TIs in detail and point out interesting trade-offs between circuit area and randomness requirements. We propose two new TIs of AES that, starting from a common previously published implementation, illustrate possible trade-offs. We provide concrete ASIC implementation results for all three designs using the same library, and we evaluate the practical security of all three designs on the same FPGA platform. Our analysis allow us to directly compare the security provided by the different trade-offs, and to quantify the associated hardware cost.

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Description: Framework is developed for estimation of power at pre register transfer level (RTL) stage for structured memory sub-systems. Power estimation model is proposed specifically targeting power consumed by clock network and interconnect. The model is validated with VCD-based simulation on back-annotated netlist of an 8 MB memory sub-system used as video RAM (VRAM) for high-end graphics applications. This methodology also forms the basis for low-power exploration driving floor plan choice, gating structure of data, and clock network. We demonstrate 57% reduction in dynamic power by using low-power techniques for the 8 MB VRAM used as frame buffer in a graphics processor. FALPEM can be extended to other applications like processor cache and ASIC designs.

Description: Ring oscillator (RO)-based physical unclonable function (PUF) is resilient against noise impacts, but its response is susceptible to temperature variations. This paper presents a low-power and small footprint hybrid RO PUF with a very high temperature stability, which makes it an ideal candidate for lightweight applications. The negative temperature coefficient of the low-power subthreshold operation of current starved inverters is exploited to mitigate the variations of differential RO frequencies with temperature. The new architecture uses conspicuously simplified circuitries to generate and compare a large number of pairs of RO frequencies. The proposed nine-stage hybrid RO PUF was fabricated using global foundry 65-nm CMOS technology. The PUF occupies only $250~ {mu }text{m}^{ {2}}$ of chip area and consumes only $32.3~ {mu }text{W}$ per challenge response pair at 1.2 V and 230 MHz. The measured average and worst-case reliability of its responses are 99.84% and 97.28%, respectively, over a wide range of temperature from −40 to 120 °C.

Description: The efficiency and cost of silicon physically unclonable function (PUF)-based applications, and in particular key generators, are heavily impacted by the level of reproducibility of the bare PUF responses (PRs) under varying operational circumstances. Error-correcting codes (ECCs) can be used to achieve near-perfect reliability, but come at a high implementation cost especially when the underlying PUF is very noisy. When designing a PUF-based key generator, a more reliable PUF will result in a less complex ECC decoder and a smaller PUF footprint, and hence, an overall more efficient implementation. This paper proposes novel insight and resulting method for reducing noise on memory-based PRs, based on adapting supply voltage ramp-up time to ambient temperature. Circuit simulations on 45 nm low-power CMOS, as well as silicon measurements are presented to validate the proposed method. Our results demonstrate that choosing an appropriate voltage ramp-up for enrollment and adapting it according to the ambient temperature at key-reconstruction is a powerful method which makes memory-based PR noise up to $3 {times }$ smaller. In addition, this paper investigates the competitiveness of integrating the proposed method in a commercial product; the investigation is done in two phases. First by determining the saved area, and second by implementing a circuit that maps the ambient temperature into an appropriate voltage ramp-up. The results show that the new system costs up to 82.1% less area while it delivers up to $3 {times }$ higher reproducibility.

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Description: Distributed nature of an MOS transistor becomes significant in high frequencies, especially in the millimeter wave band. Two types of distributed effects are encountered in an MOS transistor: the distributed effect along the transistor channel, referred as nonquasi static (NQS) effect, and the distributed effect along the gate finger. We denote the former as lateral distributed effect and the later as longitudinal distributed effect (LDE). Lateral distributed effect has been studied in many works and has been considered either accurately or approximately in the available MOS small-signal models. However, LDEs have not accurately been accounted for, except for few works in which an MOS transistor has been analyzed using transmission line approach to derive two-port ${Y}$ parameters of the transistor. Unfortunately, the two-port distributed model is not useful when the transistor is used in common gate, common drain, or cascode configurations. In this paper, we have developed a new three-port distributed model of an MOS transistor to accurately capture the LDEs. Furthermore, the proposed model can be used in conjunction with new Berkeley short-channel IGFET model (BSIM) radio frequency (RF) small-signal models, such as BSIM4.7 and BSIM6. To evaluate the proposed model, we have used Taiwan Semiconductor Manufacturing Company 90 nm RF-CMOS technology parameters. Our results show that LDE is considerably more significant than NQS effect in millimeter wave band, in the case of a short channel MOS transistor with long gate finger. This reveals the importance of LDEs in RF MOS transistor models, especially in millimeter wave band applications.

Description: Skolem and Herbrand functions are important certificates validating the truth and falsity, respectively, of quantified Boolean formulas (QBFs). They are essential in various synthesis and verification applications. Recent advancement established a linear time extraction of Skolem/Herbrand functions from QBF consensus/resolution proofs. However, the obtained functions are often excessively large and improper for practical applications. To overcome this limitation, this paper characterizes various flexibilities of QBF certificates, and exploits them for certificate simplification. Experiments show substantial reduction on QBF certificates in terms of circuit size and depth, which are of primary concerns for synthesis applications.

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Description: Today, most of the innovation in the automotive domain is in the areas of electronics and software. Modern cars have already been transformed, from largely mechanical entities, to complex embedded systems running on four wheels. High-end cars currently have around 100 electronic control units (ECUs), each with one or more, possibly multicore, processors. These ECUs communicate using different communication buses such as CAN, FlexRay, LIN, and more recently also Ethernet, and are connected to various cameras, radars, ultrasonic sensors, and also to a host of actuators. Such architectures are used to run several millions of lines of software code spanning across safety-critical, driver assistance, comfort, and entertainment related applications.

Description: Safety-relevant systems in the automotive domain often implement features such as lockstep execution for error detection, and reset and re-execution for error correction. Light-lockstep has already been adopted in some such systems due to its relatively low-implementation cost given that it does not require deep changes into nonlockstep hardware. Instead, as only off-core activities (i.e., data/addresses sent) need to be compared across different cores, light-lockstep designs are lowly intrusive. This approach has been proven sufficient to guarantee functional correctness of the system in the presence of errors in the cores, in particular in relation with certification against safety standards such as ISO26262 in the automotive domain. However, error detection in light-lockstep systems may occur long after the error actually occurs, thus jeopardizing timing guarantees, which are as critical as functional ones in hard real-time systems. In this paper, we analyze the timing behavior of errors due to transient and permanent faults in light-lockstep systems. Our results show that the time elapsed until an error is detected can be inordinately large, especially for permanent faults. Based on this observation and building upon the specific characteristics of light-lockstep systems, we propose lightly verbose (LiVe), a new mechanism to enforce the early detection of errors, due to both transient and permanent faults, thus enabling the computation of tight error detection timing bounds. We also analyze how existing mechanisms for error recovery in multicore systems increase their effectiveness when light-lockstep operates in LiVe mode in the context of mixed-criticality workloads.

Description: As the complexities of automotive systems increase, designing a system is a difficult task that cannot be done manually. In this paper, we focus on wire routing and wire sizing for weight minimization to deal with more and more connections between devices in automotive systems. The wire routing problem is formulated as a minimal Steiner tree problem with capacity constraints, and the location of a Steiner vertex is selected to add a splice which is used to connect more than two wires. We modify the Kou-Markowsky-Berman algorithm to efficiently construct Steiner trees and propose an integer linear programming (ILP) formulation to relocate Steiner vertices and satisfy capacity constraints. The ILP formulation is relaxed to a linear programming (LP) formulation which has the same optimal objective and can be solved more efficiently. Besides wire routing, wire sizing is also performed to satisfy resistance constraints and minimize the total wiring weight. To the best of our knowledge, this is the first work in the literature to formulate the automotive routing problem as a minimal Steiner tree problem with capacity constraints and perform wire routing and wire sizing for weight minimization. An industrial case study shows the effectiveness and efficiency of our algorithm which provides an efficient, flexible, and scalable approach for the design optimization of automotive systems.

Description: Idling, or running the engine when the vehicle is not moving, accounts for 13%–23% of vehicle driving time and costs billions of gallons of fuel each year. In this paper, we consider the problem of idling reduction under the uncertainty of vehicle stop time. We abstract it as a classic ski rental problem, and propose a constrained version with two statistics $mu _{B^{tt -}}$ and $q_{B^{tt +}}$ , the expected length of short stops and the probability of long stops. We develop two online algorithms, a suboptimal closed-form algorithm and an optimal numerical solution, that combine the best of the well-known deterministic and randomized schemes to minimize the worst case competitive ratio. We demonstrate the algorithms perform better than existing solutions in terms of both worst case guarantee and average case performance using simulation and real-world driving data.

Description: In order to keep pace with the growing complexity of integrated circuits (ICs), IC and system designers are increasingly using electronic system level (ESL) design tools. ESL tool sales were around $460 million in 2011. The value of the ICs designed using these tools is at least an order of magnitude more. Concurrently, advanced IC reverse engineering techniques are being developed and used by attackers. In response, several anti-reverse engineering techniques have been proposed for integration into the IC design flow. An important class of defenses hardens the controllers that orchestrate the functionality of designs generated by ESL tools. We demonstrate an attack to recover the controller in any ESL-generated design even if the controller has been hardened using state-of-the-art controller hardening techniques. The attack analyzes the unhardened parts of the controller (i.e., the controller output logic and datapath) and reconciles this information with the architectural, controller, and timing constraints implicit in and underlying all ESL design methodologies. We then propose a countermeasure that inserts decoy connections into an ESL tool-generated design to thwart reverse engineering. We introduce a security metric to quantify the effectiveness of the developed attacks and defenses. We demonstrate the attack and defenses on designs generated by state-of-the-art ESL tools.

Description: 1 Stochastic computing (SC) is an approximate computing technique that processes data in the form of long pseudorandom bit-streams which can be interpreted as probabilities. Its key advantages are low-complexity hardware and high-error tolerance. SC has recently been finding application in several important areas, including image processing, artificial neural networks, and low-density parity check decoding. Despite a long history, SC still lacks a comprehensive design methodology, so existing designs tend to be either ad hoc or based on specialized design methods. In this paper, we demonstrate a fundamental relation between stochastic circuits and spectral transforms. Based on this, we propose a general, transform-based approach to the analysis and synthesis of SC circuits. We implemented this approach in a program spectral transform use in stochastic circuit synthesis (STRAUSS), which also includes a method of optimizing stochastic number-generation circuitry. Finally, we show that the area cost of the circuits generated by STRAUSS is significantly smaller than that of previous work. 1 Parts of this paper are based on “A spectral transform approach to stochastic circuits,” which was presented at the International Conference on Computer Design, Oct. 2012 [3] .

Description: Post-silicon clock tuning elements are widely used in high-performance designs to mitigate the effects of process variations and aging. Located on clock paths to flip-flops, these tuning elements can be configured through the scan chain so that clock skews to these flip-flops can be adjusted after manufacturing. Owing to the delay compensation across consecutive register stages enabled by the clock tuning elements, higher yield and enhanced robustness can be achieved. These benefits are, nonetheless, attained by increasing die area due to the inserted clock tuning elements. For balancing performance improvement and area cost, an efficient timing analysis algorithm is needed to evaluate the performance of such a circuit. So far this evaluation is only possible by Monte Carlo simulation which is very time-consuming. In this paper, we propose an alternative method using graph transformation, which computes a parametric minimum clock period and is more than $ {10}^ {4}$ times faster than Monte Carlo simulation while maintaining a good accuracy. This method also identifies the gates that are critical to circuit performance, so that a fast analysis-optimization flow becomes possible.

Description: 3-D chips rely on massive interconnect structures, i.e., large groups of through-silicon vias coalesced with large multibit buses. We observe that wirelength optimization, a classical technique for floorplanning, is not effective while planning massive interconnects. This is due to the interconnects’ strong impact on multiple design criteria like wirelength, routability, and temperature. To facilitate early design progress of massively-interconnected 3-D chips, we propose a novel 3-D-floorplanning methodology which accounts for different types of interconnects in a unified manner. One key idea is to align cores/blocks simultaneously within and across dies, thus increasing the likelihood of successfully implementing complex and massive interconnects. While planning such interconnects, we also target fast, yet accurate, thermal management, routability, and fixed-outline floorplanning. Experimental results on Gigascale Systems Research Center and IBM-HB+ circuits demonstrate our tool’s capabilities for both planning massive 3-D interconnects and for multiobjective 3-D floorplanning in general.

Description: Multicore instruction-set simulation (MCISS) has become more and more important due to tremendous increase in number of multicore designs. To boost the speed of MCISS, one of the most effective and commonly used approaches is parallel simulation. However, timing synchronization must be applied to ensure accurate simulation results of parallel MCISS, and may induce huge synchronization overhead. In this paper, we propose a highly efficient and effective parallel MCISS approach by synchronizing timing before each synchronization function (SF) call. We improve the applicability of the state-of-the-art critical-section-level simulation approach with a generic blocking/nonblocking send/receive model covering all types of SFs. To further reduce synchronization overhead, we also introduce optimization methods such as a hybrid scheduling technique and provide an analysis algorithm that helps the designers to choose the host platform with the best simulation performance. Experiments show that the proposed approach attains a simulation speed of up to 285 MIPS, while producing accurate timing and functional results.

Description: A faulty interposer in a 2.5-D integrated circuit often results in a hefty loss as the potentially expensive known-good-dies bonded on the interposer will have to be discarded as well. To avoid such a last-minute loss during a multichip integration process, built-in self-repair (BISR) is highly valuable. Even though there have been many BISR schemes in the literature, the proposed method offers a number of distinct features. First, it can target not only catastrophic faults, but also timing faults. Second, it can be applied to general multi-pin interconnects and it can be applied to repair an interposer with multiple faulty interconnects. Third, it can perform the test-and-then-repair flow on-the-fly, and thereby eliminating the overhead of extra repair storage incurred in previous methods.

Description: Modern very large-scale integration (VLSI) layout databases routinely consist of 10e15 edges, and thus problems of information retrieval, intellectual property (IP) inventory control, tampering detection, IP infringement detection, data tagging, and database version control, are extremely computationally intensive. All these tasks can be reduced to the problem of copy detection, and in this paper, we propose a canonical hash function for VLSI layout datasets which can be used for efficient copy detection and signature generation. The proposed signature is independent of the ordering of the layout elements, their tessellation, resolution, and even vertex count. These parameters, which do not contribute to the final wafer image, increase the entropy of the data and thus standard hash functions such as message digest (MD5) or secure hash algorithm (SHA), are not suitable for this problem of VLSI layout hashing. In this paper, a novel, entropy reduced hash function is developed which can be used to alleviate the above mentioned problems of physical IP management. The proposed method has ${O(n log n + k)}$ time complexity, and $ {O(sqrt {n})}$ memory complexity, where $ {n}$ is the number of edges in the input layout, and $ {k}$ is the number of intersections between edges. The proposed system has been implemented, and computational results validating our approach are also provided.

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Description: This paper introduces a novel test data compression scheme, which is primarily devised for low-power test applications. It is based on a fundamental observation that in addition to low test cube fill rates, a very few specified bits, necessary to detect a fault, are actually irreplaceable, whereas the remaining ones can be placed in alternative locations (scan cells). The former assignments are used to create residual test cubes and, subsequently, test templates. They control a power-aware decompressor and guide automatic test pattern generation to produce highly compressible test patterns through finding alternative assignments. The proposed approach reduces, in a user-controlled manner, scan shift-in switching rates with minimal hardware modifications. It also elevates compression ratios to values typically unachievable through conventional low-power reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

Description: 3-D integration using through-silicon vias offers many benefits, such as high bandwidth, low power, and small footprint. However, test complexity and test cost are major concerns for 3-D ICs. Recent work on the optimization of 3-D test architectures to reduce test cost suffer from the drawback that they ignore potential uncertainties in input parameters; they consider only a single point in the input-parameter space. In realistic scenarios, the assumed values for parameters such as test power and pattern count of logic cores, which are used for optimizing the test architecture for a die, may differ from the actual values that are known only after the design stage. In a 3-D setting, a die can be used in multiple stacks with different properties. As a result, the originally designed test architecture is no longer optimal, which leads to an undesirable increase in the test cost. We propose an optimization approach that takes uncertainties in input parameters into account and provides a solution that is efficient in the presence of input-parameter variations. We formulate a mathematical model for the robust test-architecture optimization problem, and propose an efficient heuristic to solve the problem even for large designs in reasonable time. The proposed optimization framework is evaluated using the ITC’02 SoC benchmarks and we show that robust solutions are superior to single-point solutions in terms of average test time when there are uncertainties in the values of input parameters.

Description: Formal verification of a control system can be performed by checking if a model of its dynamical behavior conforms to temporal requirements. Unfortunately, adoption of formal verification in an industrial setting is a formidable challenge as design requirements are often vague, nonmodular, evolving, or sometimes simply unknown. We propose a framework to mine requirements from a closed-loop model of an industrial-scale control system, such as one specified in Simulink. The input to our algorithm is a requirement template expressed in parametric signal temporal logic: a logical formula in which concrete signal or time values are replaced with parameters. Given a set of simulation traces of the model, our method infers values for the template parameters to obtain the strongest candidate requirement satisfied by the traces. It then tries to falsify the candidate requirement using a falsification tool. If a counterexample is found, it is added to the existing set of traces and these steps are repeated; otherwise, it terminates with the synthesized requirement. Requirement mining has several usage scenarios: mined requirements can be used to formally validate future modifications of the model, they can be used to gain better understanding of legacy models or code, and can also help enhancing the process of bug finding through simulations. We demonstrate the scalability and utility of our technique on three complex case studies in the domain of automotive powertrain systems: a simple automatic transmission controller, an air-fuel controller with a mean-value model of the engine dynamics, and an industrial-size prototype airpath controller for a diesel engine. We include results on a bug found in the prototype controller by our method.

Description: 3-D stacked integrated circuit (IC) technology based on through-silicon vias (TSVs) provides numerous advantages as compared to traditional 2-D-ICs. A potential application is memory stacked on logic, providing enhanced throughput, and reduced latency and power consumption. However, testing the TSV interconnects between the two dies is challenging as both memory and logic dies might come from different providers. Currently, no standard exists and the proposed solutions fail to address dynamic and time-critical faults (at speed testing). In addition, memory vendors have not been in favor to put additional design-for-testability structures such as Joint Test Action Group for interconnect testing on their memory devices. This paper proposes a new memory-based interconnect test (MBIT) approach for 3-D memories stacked on logic (e.g., CPUs). A structural approach is used to develop fault models, their detection conditions, and test and diagnosis patterns. The test patterns are applied by read and write instructions to the memory and are validated by a case study where a 3-D memory is assumed to be stacked on a MIPS64 processor. The main benefits of the MBIT approach are: 1) zero area overhead; 2) the ability to detect both static and dynamic faults and perform at speed testing; 3) flexibility in applying any test pattern, as this can be executed by the CPU on the logic die; 4) extreme short test execution time; and 5) the ability to perform interconnect diagnosis.

Description: Quantum mechanical phenomena such as phase shifts, superposition, and entanglement show promise in use for computation. Suitable technologies for the modeling and design of quantum computers and other information processing techniques that exploit quantum mechanical principles are in the range of vision. Quantum algorithms that significantly speed up the process of solving several important computation problems have been proposed in the past. The most common representation of quantum mechanical phenomena are transformation matrices. However, the transformation matrices grow exponentially with the size of a quantum system and, thus, pose significant challenges for efficient representation and manipulation of quantum functionality. In order to address this problem, first approaches for the representation of quantum systems in terms of decision diagrams have been proposed. One very promising approach is given by Quantum Multiple-Valued Decision Diagrams (QMDDs) which are able to efficiently represent transformation matrices and also inherently support multiple-valued basis states offered by many physical quantum systems. However, the initial proposal of QMDDs was lacking in a formal basis and did not allow, e.g., the change of the variable order—an established core functionality in decision diagrams which is crucial for determining more compact representations. Because of this, the full potential of QMDDs or decision diagrams for quantum functionality in general has not been fully exploited yet. In this paper, we present a refined definition of QMDDs for the general quantum case. Furthermore, we provide significantly improved computational methods for their use and manipulation and show that the resulting representation satisfies important criteria for a decision diagram, i.e., compactness and canonicity. An experimental evaluation confirms the efficiency of QMDDs.

Description: Transistor count minimization is an important goal as very-large-scale integration technology approaches its technical and physical limits. In this paper, we present a computer-aided design synthesis tool that tries to minimize the number of transistors required to implement a given multiple-output logic function. The proposed transistor-level synthesis approach goes beyond the traditional series-parallel design style and allows for extensive bridging. It starts from a sum-of-products expression for each output, allowing also for don’t care terms, and produces a transistor network with a small number of transistors to implement all outputs jointly under a user-specified bound on the number of transistors in series to avoid long charge/discharge paths. Experimental results on previously examined multioutput functions and case studies (full adder, Gray/binary counter, and seven-segment display) demonstrate the benefit of the approach.

Description: Many modern applications exhibit a dynamic and nonstationary behavior, with certain characteristics in one phase of their execution, which change as the application enters new phases, in a manner unpredictable at design-time. In order to meet the demands of such applications, it is important to have adaptive and self-reconfiguring hardware platforms, coupled with intelligent on-line optimization algorithms, that together can adjust to the run-time requirements. Partially dynamically reconfigurable field programmable gate array architectures offer both high performance and flexibility. Despite these potential advantages, the challenges faced by designers trying to set-up a functioning system are still significant, mainly because of the still immature design tools and limited device drivers. We propose a complete framework, based on Xilinx’s commercial design suite, that enables an application designer to leverage the advantages of partial dynamic reconfiguration with minimal effort. Our IP-based architecture, together with the comprehensive application programming interface, can be employed to accelerate an application by dynamically scheduling hardware prefetches. Moreover, a piecewise linear predictor is used to capture correlations and predict the hardware modules that will generate the highest performance improvement. Our evaluation comprises of extensive simulations, as well as a complete implementation of the smallest univalue segment assimilating nucleus image processing application on the ML605 board from Xilinx. The measurements show a significant reduction of the expected execution time compared to previous state-of-the-art prefetching algorithms, with only a minor energy overhead.

Description: Compact modeling of phase-locked loop (PLL) frequency synthesizer is proposed to reduce transient phase noise and jitter simulation time. Conventional small-signal noise assumption based frequency-domain simulation approach produces inaccurate results for nonlinear PLLs. Accurate analysis of nonlinear PLL are possible through time-domain, or transient noise simulation but time-domain simulation is computation-intensive and time-consuming. This paper presents a practical solution for transient phase noise and jitter analysis using compact modeling techniques. It features an autoregressive moving average process modeled voltage-controlled oscillator with fractional calculus and wavelet transform for phase noise decomposition and reconstruction, thereby reducing the phase noise and jitter simulation time to 25.8% of the transistor-level simulation with 0.4 dB @ 1 MHz phase noise error and 0.3 ps long-term jitter error for a 2 GHz PLL frequency synthesizer in a 65 nm CMOS process.