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  • Articles  (5)
  • fault simulation
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  • Springer  (5)
  • American Chemical Society
  • BioMed Central
  • 2025-2025
  • 2020-2024
  • 2020-2022
  • 2010-2014
  • 2005-2009
  • 1995-1999  (5)
  • 1998  (5)
  • Electrical Engineering, Measurement and Control Technology  (5)
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  • Articles  (5)
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  • Springer  (5)
  • American Chemical Society
  • BioMed Central
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  • 2025-2025
  • 2020-2024
  • 2020-2022
  • 2010-2014
  • 2005-2009
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  • 1
    Electronic Resource
    Electronic Resource
    Fault Modeling and Simulation Using VHDL-AMS (1998)
    Springer
    Analog integrated circuits and signal processing 16 (1998), S. 141-155 
    Details
    ISSN: 1573-1979
    Keywords: analog simulation ; analog test ; fault simulation ; fault modeling ; analog VHDL
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Fault simulation is an accepted part of the test generation procedure for digital circuits. With complex analog and mixed-signal integrated circuits, such techniques must now be extended. Analog simulation is slow and fault simulation can be prohibitively expensive because of the large number of potential faults. We describe how the number of faults to be simulated in an analog circuit can be reduced by fault collapsing, and how the simulation time can be reduced by behavioral modeling of fault-free and faulty circuit blocks. These behavioral models can be implemented in SPICE or in VHDL-AMS and we discuss the merits of each approach. VHDL-AMS does potentially offer advantages in tackling this problem, but there are a number of computational difficulties to be overcome.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008267723105
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    Paper (German National Licenses)
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  • 2
    Electronic Resource
    Electronic Resource
    Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits (1998)
    Springer
    Journal of electronic testing 12 (1998), S. 239-254 
    Details
    ISSN: 1573-0727
    Keywords: delay test ; fault simulation ; path-delay faults ; transition faults ; statistical fault analysis
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract We present a technique to statistically estimate path-delay fault coverage for synchronous sequential circuits. We perform fault-free simulation using a multivalue algebra and accumulate signal transition statistics, from which we calculate controllabilities of all signals and sensitization probabilities for all gates and flip-flops. We use a rated clock testing model where all time frames operate at the rated clock. We obtain path observabilities either by enumerating paths in the all-paths method, or by a nonenumerative method considering only the longest paths. The path-delay fault detectability is the product of observabilities of signals on paths from primary inputs (PIs) or pseudo-primary inputs (PPIs) to primary outputs (POs) or pseudo-primary outputs (PPOs), and the controllability on the corresponding PI or PPI. We use the optimistic update rule of Bose et al. for updating latches during logic simulation. When compared with exact fault simulation, the average absolute deviation in our statistical fault coverage estimation technique is 1.23% and the very worst absolute deviation was 6.59%. On average, our method accelerates delay fault coverage computation four times over an exact path delay fault simulator.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008228817698
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  • 3
    Electronic Resource
    Electronic Resource
    Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools (1998)
    Springer
    Journal of electronic testing 13 (1998), S. 315-319 
    Details
    ISSN: 1573-0727
    Keywords: cell fault model (CFM) ; stuck-at fault model ; fault simulation ; test pattern generation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Cell Fault Model (CFM) is a well-adopted functional fault model used for cell-based circuits. Despite of the wide adoption of CFM, no test tool is available for the estimation of CFM testability. The vast majority of test tools are based on the single stuck-at fault model. In this paper we introduce a method to calculate the CFM testability of a cell-based circuit using any single stuck-at fault based test tool. Cells are substituted by equivalent cells and Test Generation and Fault Simulation for CFM are emulated by Test Generation and Fault Simulation for a set of single stuck-at faults of the equivalent cells. The equivalent cell is constructed from the original cell with a simple procedure, with no need of knowledge of gate-level implementation, or its function. With the proposed methodology, the maturity and effectiveness of stuck-at fault based tools is used in testing of digital circuits, with respect to Cell Fault Model, without developing new tools.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008389920806
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  • 4
    Electronic Resource
    Electronic Resource
    Behavioral Level Noise Modeling and Jitter Simulation of Phase-Locked Loops with Faults Using VHDL-AMS (1998)
    Springer
    Journal of electronic testing 13 (1998), S. 7-17 
    Details
    ISSN: 1573-0727
    Keywords: analog test ; fault modeling ; fault simulation ; noise ; jitter ; behavioral fault modeling
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract It is important to predict noise at the early stages of a top-down design. In this paper, we propose a methodology to model phase noise or jitter, a key specification for phase-locked loops, using a mixed-signal hardware description language, and to simulate the effects of catastrophic faults on the phase jitter at the behavioral level. In contrast to existing approaches which either require dedicated noise simulators or postpone noise and fault simulation to the transistor level, we have successfully demonstrated that noise in a voltage-controlled oscillator (VCO), power supply noise, and their effects on the overall phase jitter within a faulty PLL can be modeled and simulated earlier on at the behavioral level. Our simulation results are consistent with experimentally-verified theoretical predictions.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008329031457
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  • 5
    Electronic Resource
    Electronic Resource
    Growth and Characterization of TlBaCaCuO Thin Films (1998)
    Springer
    Journal of superconductivity 11 (1998), S. 135-138 
    Details
    ISSN: 1572-9605
    Keywords: Superconductor ; thallium ; Tl-Ba-Ca-Cu-O ; film ; growth
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology , Physics
    Notes: Abstract We discuss two methods tor the ex-situ furnace growth of pure TIBaCaCuO superconducting thin films on LaAlO3(100) substrates. The traditional approach of “crucible processing” is used to grow high-quality films of several of the TIBaCaCuO phases. “Two-zone processing” promises greater thermodynamic control, yet film properties from optimized films are not as good as those grown from crucibles. The transport kinetics of Tl-oxide vapor from a source to the film surface appears to be a dominant factor. The best results are from single-phase Tl-1212 and Tl-2212 thin films. Tc's are high and sharp, Jc's 〉 1 × 107 A/cm2 at 5 K, and surface morphologies are relatively smooth.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1022687408646
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