A 2.5 ns 8×8-b parallel multiplier using 0.5 μm GaAs/GaAlAs heterostructure field effect transistors

Abstract

To increase performance of GaAs LSI digital circuits, a 0.5 μm recessed gate process has been developed and utilized for an 8×8-b parallel multiplier. The chip contains about 3000 heterostructure field effect transistors and has a power consumption of 1.5 W. The best results of the maximum multiplication time measured were below 2.5 nsec.