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Minimal Power Latch for Single-Slope ADCsColumn-parallel analog-to-digital converters (ADCs) for imagers involve simultaneous operation of many ADCs. Single-slope ADCs are well adapted to this use because of their simplicity. Each ADC contains a comparator, comparing its input signal level to an increasing reference signal (ramp). When the ramp is equal to the input, the comparator triggers a latch that captures an encoded counter value (code). Knowing the captured code, the ramp value and hence the input signal are determined. In a column-parallel ADC, each column contains only the comparator and the latches; the ramp and code generation are shared. In conventional latch or flip-flop circuits, there is an input stage that tracks the input signal, and this stage consumes switching current every time the input changes. With many columns, many bits, and high code rates, this switching current can be substantial. It will also generate noise that may corrupt the analog signals. A latch was designed that does not track the input, and consumes power only at the instant of latching the data value. The circuit consists of two S-R (set-reset) latches, gated by the comparator. One is set by high data values and the other by low data values. The latches are cross-coupled so that the first one to set blocks the other. In order that the input data not need an inversion, which would consume power, the two latches are made in complementary polarity. This requires complementary gates from the comparator, instead of complementary data values, but the comparator only triggers once per conversion, and usually has complementary outputs to begin with. An efficient CMOS (complementary metal oxide semiconductor) implementation of this circuit is shown in the figure, where C is the comparator output, D is the data (code), and Q0 and Q1 are the outputs indicating the capture of a zero or one value. The latch for Q0 has a negative-true set signal and output, and is implemented using OR-AND-INVERT logic, while the latch for Q1 uses positive- true signals and is implemented using AND-OR-INVERT logic. In this implementation, both latches are cleared when the comparator is reset. Two redundant transistors are removed from the reset side of each latch, making for a compact layout. CMOS imagers with column-parallel ADCs have demonstrated high performance for remote sensing applications. With this latch circuit, the power consumption and noise can be further reduced. This innovation can be used in CMOS imagers and very-low-power electronics
Document ID
20130014441
Acquisition Source
Jet Propulsion Laboratory
Document Type
Other - NASA Tech Brief
External Source(s)
http://www.techbriefs.com/component/content/article/16959
Authors
Hancock, Bruce R. (California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
August 27, 2013
Publication Date
August 1, 2013
Publication Information
Publication: NASA Tech Briefs, August 2013
Subject Category
Man/System Technology And Life Support
Report/Patent Number
NPO-48007
Distribution Limits
Public
Copyright
Public Use Permitted.

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IDRelationTitle20130014433Collected WorksNASA Tech Briefs, August 2013
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