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Integrating Cache Performance Modeling and Tuning Support in Parallelization ToolsWith the resurgence of distributed shared memory (DSM) systems based on cache-coherent Non Uniform Memory Access (ccNUMA) architectures and increasing disparity between memory and processors speeds, data locality overheads are becoming the greatest bottlenecks in the way of realizing potential high performance of these systems. While parallelization tools and compilers facilitate the users in porting their sequential applications to a DSM system, a lot of time and effort is needed to tune the memory performance of these applications to achieve reasonable speedup. In this paper, we show that integrating cache performance modeling and tuning support within a parallelization environment can alleviate this problem. The Cache Performance Modeling and Prediction Tool (CPMP), employs trace-driven simulation techniques without the overhead of generating and managing detailed address traces. CPMP predicts the cache performance impact of source code level "what-if" modifications in a program to assist a user in the tuning process. CPMP is built on top of a customized version of the Computer Aided Parallelization Tools (CAPTools) environment. Finally, we demonstrate how CPMP can be applied to tune a real Computational Fluid Dynamics (CFD) application.
Document ID
20020073380
Acquisition Source
Ames Research Center
Document Type
Preprint (Draft being sent to journal)
Authors
Waheed, Abdul (MRJ Technology Solutions, Inc. Moffett Field, CA United States)
Yan, Jerry (MRJ Technology Solutions, Inc. Moffett Field, CA United States)
Saini, Subhash
Date Acquired
September 7, 2013
Publication Date
January 1, 1998
Subject Category
Computer Operations And Hardware
Meeting Information
Meeting: PPoPP 1999
Location: Atlanta, GA
Country: United States
Start Date: May 1, 1999
Funding Number(s)
PROJECT: RTOP 519-40-12
CONTRACT_GRANT: NAS2-14303
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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