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Vergleich verschiedener planarer Passivierungstechniken für Halbleiterleistungsbauelemente

Comparison of different planar passivation techniques for semiconductor power devices

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Übersicht

Für die Entwicklung einer optimalen Planar-passivierung von Halbleiterleistungsbauelementen mit Sperrspannungen von 1600 V wird ein Vergleich verschiedener Strukturen anhand zweidimensionaler numerischer Simulationen durchgeführt.

Contents

Different passivation techniques for planar semiconductor power devices with blocking voltages of 1600 V are studied using two-dimensional numerical simulations.

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Authors and Affiliations

  1. AEG Forschungsinstitut, Goldsteinstr. 235, D-6000, Frankfurt 71, Bundesrepublik Deutschland

    K. -P. Brieger,  J. Korec &  B. Thomas

Authors
  1. K. -P. Brieger
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  2. J. Korec
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  3. B. Thomas
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Herrn Prof. Dr. phil. nat. W. Gerlach zum 60. Geburtstag gewidmet

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Brieger, K.P., Korec, J. & Thomas, B. Vergleich verschiedener planarer Passivierungstechniken für Halbleiterleistungsbauelemente. Archiv f. Elektrotechnik 72, 89–94 (1989). https://doi.org/10.1007/BF01573642

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  • DOI: https://doi.org/10.1007/BF01573642

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