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Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantationProgress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.
Document ID
19800018104
Acquisition Source
Legacy CDMS
Document Type
Contractor Report (CR)
Authors
Woo, D. S. (RCA Solid State Technology Center Somerville, NJ, United States)
Date Acquired
September 4, 2013
Publication Date
August 1, 1977
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
PRRL-77-CR-40
NASA-CR-150607
Accession Number
80N26603
Funding Number(s)
CONTRACT_GRANT: NAS8-31986
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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