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  • Other Sources  (9)
  • 1
    Publication Date: 2011-08-18
    Description: A fault model and a system model are necessary to assess the tolerance or resilience of a digital system to lightning-induced transients. It is noted that these models are usually developed separately. A new approach is outlined here for this assessment problem which combines the fault and system models into an overall model. With this approach, referred to as the containment set approach, an assessment of the effects of lightning-induced transients can be made in terms of a state transition matrix. This matrix can be generated by means of fault injection experiments. In addition, certain nonredundancy-oriented design alternatives to the achievement of lightning-induced transient tolerance in digital systems are indicated by the containment set approach.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
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  • 2
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    In:  Other Sources
    Publication Date: 2019-06-27
    Description: In the present paper, the concept of a hybrid fault situation is introduced, which specifies bounded combinations of permanently faulty and intermittently faulty units in a system. The general class of hybrid fault situations includes, as special cases, the all permanent fault case and the unrestricted intermittent fault case, which have been previously considered with PMC models. An approach compatible with the diagnosis of permanent fault situations is then applied to the diagnosis of hybrid fault situation. The motivation for doing so is the common practice of testing for the presence of intermittent faults in systems by means of repeated applications of tests that are designed for the detection of permanent faults. The testing assignment of PMC models of system is characterized, and interrelationships between the number of intermittently and permanently faulty units that can be diagnosed is established.
    Keywords: COMPUTER OPERATIONS AND HARDWARE
    Type: IEEE Transactions on Computers; C-29; June 198
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  • 3
    Publication Date: 2019-06-28
    Description: Containment set techniques are applied to 8085 microprocessor controllers so as to transform a typical control system into a slightly modified version, shown to be crashproof: after the departure of the intermittent/transient fault, return to one proper control algorithm is assured, assuming no permanent faults occur.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: NASA-CR-169022 , NAS 1.26:169022
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  • 4
    Publication Date: 2019-06-28
    Description: The modeling and analysis of transient faults in microprocessor based controllers are discussed. Such controllers typically consist of a microprocessor, read only memory storing and application program, random access memory for data storage, and input/output devices for external communications. The effects of transient faults on the performance of the controller are reviewed. An instruction level perspective of performance is taken which is the basis of a useful high level program state description of the microprocessor controller. A transition matrix is defined which determines the controller's response to transient fault arrivals.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: NASA-CR-165713
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  • 5
    Publication Date: 2019-06-27
    Description: An overview of an approach for diagnosing intermittent/transient (I/T) faults is presented. The development of an interrelated theory and experimental methodology to be used in a laboratory situation to measure the capability of a fault tolerant computing system to diagnose I/T faults, is discussed. To the extent that such diagnosing capability is important to reliability in fault tolerant computing systems, this theory and supporting methodology serves as a foundation for validation efforts.
    Keywords: SYSTEMS ANALYSIS
    Type: NASA-CR-159229
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  • 6
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    In:  Other Sources
    Publication Date: 2019-06-27
    Description: The fault diagnosis capabilities of systems composed of interconnected units capable of testing each other are studied for the case of systems with intermittent faults. A central role is played by the concept of t(i)-fault diagnosability. A system is said to be t(i)-fault diagnosable when it is such that if no more than t(i) units are intermittently faulty then a fault-free unit will never be diagnosed as faulty and the diagnosis at any time is at worst incomplete. Necessary and sufficient conditions for t(i)-fault diagnosability are proved, and bounds for t(i) are established. The conditions are in general more restrictive than those for permanent-fault diagnosability. For intermittent faults there is only one testing strategy (repetitive testing), and consequently only one type of intermittent-fault diagnosable system.
    Keywords: COMPUTER OPERATIONS AND HARDWARE
    Type: IEEE Transactions on Computers; C-27; June 197
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  • 7
    Publication Date: 2019-06-28
    Description: An approach to the fault analysis of digital systems is proposed which combines faults, hardware, and software into one overall model. The model is useful for the consideration of intermittent/transient faults, and supports a new method, based on the concept of a containment set, for realizing transient fault tolerance without massive redundancy. The model also serves as the basis for a new approach to system fault tolerance evaluation and validation using a transition matrix defined in terms of the containment set. The application of upset theory to the design of transient fault-tolerant microprocessor controllers is discussed.
    Keywords: CYBERNETICS
    Type: IEEE Transactions on Computers; C-31; July 198
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  • 8
    Publication Date: 2019-06-27
    Description: An overview of the intermittent/transient (IT) fault study is presented. An interval survivability evaluation of digital systems for IT faults is discussed along with a method for detecting and diagnosing IT faults in digital systems.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: NASA-CR-153743
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  • 9
    Publication Date: 2019-06-28
    Description: Accomplishments and directions for further research aimed at developing methods for assessing a candidate design of an avionic computer with respect to susceptability to lightning upset are reported. Emphasis is on fault tolerant computers. Both lightning stress and shielding are covered in a review of the electromagnetic environment. Stress characterization, system characterization, upset detection, and positive and negative design features are considered. A first cut theory of comparing candidate designs is presented including tests of comparative susceptability as well as its analysis and simulation. An approach to lightning induced transient fault effects is included.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
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