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  • 1
    Electronic Resource
    Electronic Resource
    Springer
    International journal of parallel programming 21 (1992), S. 421-448 
    ISSN: 1573-7640
    Keywords: Dataflow architecture ; loop scheduling ; storage allocation ; polynomial algorithm
    Source: Springer Online Journal Archives 1860-2000
    Topics: Computer Science
    Notes: Abstract In this paper, we consider the optimal loop scheduling and minimum storage allocation problems based on the argument-fetching dataflow architecture model. Under the argument-fetching model, the result generated by a node is stored in a unique location which is addressable by its successors. The main contribution of this paper includes: for loops containing no loop-carried dependences, we prove that the problem of allocating minimum storage required to support rate-optimal loop scheduling can be solved in polynomial time. The polynomial time algorithm is based on the fact that the constraint matrix in the formulation is totally unimodular. Since the instruction processing unit of an argument-fetching dataflow architecture is very much like a conventional processor architecture without a program counter, the solution of the optimal loop storage allocation problem for the former will also be useful for the latter.
    Type of Medium: Electronic Resource
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  • 2
    Electronic Resource
    Electronic Resource
    Springer
    International journal of parallel programming 26 (1998), S. 313-344 
    ISSN: 1573-7640
    Keywords: MODULO SCHEDULING ; SOFTWARE PIPELINING ; REGISTERS ; ENUMERATION ; INSTRUCTION-LEVEL PARALLELISM
    Source: Springer Online Journal Archives 1860-2000
    Topics: Computer Science
    Notes: Abstract Resource-constrained software-pipelining has played an increasingly significant role in exploiting instruction-level parallelism and has drawn intensive academic and industrial interest. The challenge is to find a schedule which is optimal : i.e., given the data dependence graph (DDG) for a loop, find the fastest possible schedule under given resource constraints while keeping register usage minimal. This paper proposes a novel enumeration based modulo scheduling approach to solve this problem. The proposed approach does not require any awkward reworking of constraints into linear form and employs a realistic register model. The set of schedules enumerated also allows us to characterize the schedule space and address questions such as whether schedules using a small number of registers tend to require a large number of function units. The proposed approach has been implemented under the MOST testbed at McGill University. Experimental results on more than 1000 loops from popular benchmark programs show that enumeration is generally faster at obtaining optimal schedules than integer linear programming approaches. Compared to Huff's Slack Scheduling , enumeration found a faster schedule for almost 15% of loops, with a mean improvement of 18%. 10% of the remaining loops required fewer registers under enumeration, with a mean reduction of 16%.
    Type of Medium: Electronic Resource
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