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  • COMPUTER OPERATIONS AND HARDWARE  (2)
  • dataflow programming  (2)
  • 1
    Electronic Resource
    Electronic Resource
    Springer
    Formal methods in system design 11 (1997), S. 41-70 
    ISSN: 1572-8102
    Keywords: dataflow programming ; synchronous dataflow ; memory management ; multirate signal processing algorithms ; SDF compiler ; on-chip memory ; minimum cuts ; dynamic programming
    Source: Springer Online Journal Archives 1860-2000
    Topics: Computer Science
    Notes: Abstract In this paper, we formally develop techniques that minimize the memory requirements of a target program when synthesizing software from dataflow descriptions of multirate signal processing algorithms. The dataflow programming model that we consider is the synchronous dataflow (SDF) model [21], which has been used heavily in DSP design environments over the past several years. We first focus on the restricted class of well-ordered SDF graphs. We show that while extremely efficient techniques exist for constructing minimum code size schedules for well-ordered graphs, the number of distinct minimum code size schedules increases combinatorially with the number of vertices in the input SDF graph, and these different schedules can have vastly different data memory requirements. We develop a dynamic programming algorithm that computes the schedule that minimizes the data memory requirement from among the schedules that minimize code size, and we show that the time complexity of this algorithm is cubic in the number of vertices in the given well-ordered SDF graph. We present several extensions to this dynamic programming technique to more general scheduling problems, and we present a heuristic that often computes near-optimal schedules with quadratic time complexity. We then show that finding optimal solutions for arbitrary acyclic graphs is NP-complete, and present heuristic techniques that jointly minimize code and data size requirements. We present a practical example and simulation data that demonstrate the effectiveness of these techniques.
    Type of Medium: Electronic Resource
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  • 2
    Electronic Resource
    Electronic Resource
    Springer
    Formal methods in system design 5 (1994), S. 183-205 
    ISSN: 1572-8102
    Keywords: dataflow programming ; multirate signal processing ; optimizing compilers
    Source: Springer Online Journal Archives 1860-2000
    Topics: Computer Science
    Notes: Abstract The synchronous dataflow (SDF) programming paradigm has been used extensively in design environments for multirate signal processing applications. In this paradigm, the repetition of computations is specified by the relative rates at which the computations consume and produce data. This implicit specification of iteration allows a compiler to easily explore alternative nested loop structures for the target code with respect to their effects on code size, buffering requirements and throughput. In this paper, we develop important relationships between the SDF description of an algorithm and the range of looping structures offered by this description, and we discuss how to improve code efficiency by applying these relationships.
    Type of Medium: Electronic Resource
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  • 3
    Publication Date: 2019-06-28
    Description: As disk arrays become widely used, tools for understanding and analyzing their performance become increasingly important. In particular, performance models can be invaluable in both configuring and designing disk arrays. Accurate analytic performance models are desirable over other types of models because they can be quickly evaluated, are applicable under a wide range of system and workload parameters, and can be manipulated by a range of mathematical techniques. Unfortunately, analytical performance models of disk arrays are difficult to formulate due to the presence of queuing and fork-join synchronization; a disk array request is broken up into independent disk requests which must all complete to satisfy the original request. We develop, validate, and apply an analytic performance model for disk arrays. We derive simple equations for approximating their utilization, response time, and throughput. We then validate the analytic model via simulation and investigate the accuracy of each approximation used in deriving the analytical model. Finally, we apply the analytical model to derive an equation for the optimal unit of data striping in disk arrays.
    Keywords: COMPUTER OPERATIONS AND HARDWARE
    Type: NASA-CR-189964 , NAS 1.26:189964 , UCB/CSD-91/660
    Format: application/pdf
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  • 4
    Publication Date: 2019-06-28
    Description: The performance of a variety of parity placement schemes are defined and investigated to demonstrate that, at relatively large request sizes of hundreds of kilobytes, the choice of parity placement significantly affects performance (20 to 30 percent for the disk array configurations that are common today). It is shown that the left-symmetric, extended-left-symmetric and flat-left-symmetric are the best RAID level 5 parity placements. The placement with the highest read performance, flat-left-symmetric, has the lowest write performance, while the placement with the lowest read performance, left-symmetric, has the highest write performance. Suggestions for optimizing parity placements are included.
    Keywords: COMPUTER OPERATIONS AND HARDWARE
    Format: text
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