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  • 1
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    Lower-Dark-Current, Higher-Blue-Response CMOS Imagers (2008)
    In:  CASI
    Details
    Publication Date: 2019-07-12
    Description: Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.
    Keywords: Electronics and Electrical Engineering
    Type: NPO-41224 , NASA Tech Briefs, August 2008; 14-15
    Format: application/pdf
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    NASA TECHNICAL REPORTS
  • 2
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    Fast, High-Precision Readout Circuit for Detector Arrays (2013)
    In:  CASI
    Details
    Publication Date: 2019-08-13
    Description: The GEO-CAPE mission described in NASA's Earth Science and Applications Decadal Survey requires high spatial, temporal, and spectral resolution measurements to monitor and characterize the rapidly changing chemistry of the troposphere over North and South Americas. High-frame-rate focal plane arrays (FPAs) with many pixels are needed to enable such measurements. A high-throughput digital detector readout integrated circuit (ROIC) that meets the GEO-CAPE FPA needs has been developed, fabricated, and tested. The ROIC is based on an innovative charge integrating, fast, high-precision analog-to-digital circuit that is built into each pixel. The 128128-pixel ROIC digitizes all 16,384 pixels simultaneously at frame rates up to 16 kHz to provide a completely digital output on a single integrated circuit at an unprecedented rate of 262 million pixels per second. The approach eliminates the need for off focal plane electronics, greatly reducing volume, mass, and power compared to conventional FPA implementations. A focal plane based on this ROIC will require less than 2 W of power on a 11-cm integrated circuit. The ROIC is fabricated of silicon using CMOS technology. It is designed to be indium bump bonded to a variety of detector materials including silicon PIN diodes, indium antimonide (InSb), indium gallium arsenide (In- GaAs), and mercury cadmium telluride (HgCdTe) detector arrays to provide coverage over a broad spectral range in the infrared, visible, and ultraviolet spectral ranges.
    Keywords: Electronics and Electrical Engineering
    Type: NPO-47320 , NASA Tech Briefs, September 2013; 6
    Format: application/pdf
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  • 3
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    A back-illuminated megapixel CMOS image sensor (2005)
    In:  Other Sources
    Details
    Publication Date: 2019-07-13
    Description: In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.
    Keywords: Electronics and Electrical Engineering
    Type: IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors; Jun 09, 2005 - Jun 11, 2005; Karuizawa; Japan
    Format: text
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  • 4
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    Mapping Electrical Crosstalk in Pixelated Sensor Arrays (2017)
    In:  CASI
    Details
    Publication Date: 2019-08-26
    Description: The effects of inter pixel capacitance in a pixilated array may be measured by first resetting all pixels in the array to a first voltage, where a first image is read out, followed by resetting only a subset of pixels in the array to a second voltage, where a second image is read out, where the difference in the first and second images provide information about the inter pixel capacitance. Other embodiments are described and claimed.
    Keywords: Electronics and Electrical Engineering
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  • 5
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    Analog bus driver and multiplexer (2012)
    In:  CASI
    Details
    Publication Date: 2019-08-26
    Description: For a source-follower signal chain, the ohmic drop in the selection switch causes unacceptable voltage offset, non-linearity, and reduced small signal gain. For an op amp signal chain, the required bias current and the output noise rises rapidly with increasing the array format due to a rapid increase in the effective capacitance caused by the Miller effect boosting up the contribution of the bus capacitance. A new switched source-follower signal chain circuit overcomes limitations of existing op-amp based or source follower based circuits used in column multiplexers and data readout. This will improve performance of CMOS imagers, and focal plane read-out integrated circuits for detectors of infrared or ultraviolet light.
    Keywords: Electronics and Electrical Engineering
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  • 6
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    Method and Circuit for Injecting a Precise Amount of Charge onto a Circuit Node (2016)
    In:  CASI
    Details
    Publication Date: 2019-08-26
    Description: A method and circuit for injecting charge into a circuit node, comprising (a) resetting a capacitor's voltage through a first transistor; (b) after the resetting, pre-charging the capacitor through the first transistor; and (c) after the pre-charging, further charging the capacitor through a second transistor, wherein the second transistor is connected between the capacitor and a circuit node, and the further charging draws charge through the second transistor from the circuit node, thereby injecting charge into the circuit node.
    Keywords: Electronics and Electrical Engineering
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  • 7
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    Increasing the dynamic range of CMOS photodiode imagers (2007)
    In:  CASI
    Details
    Publication Date: 2019-08-17
    Description: A multiple-step reset process and circuit for resetting a voltage stored on a photodiode of an imaging device. A first stage of the reset occurs while a source and a drain of a pixel source-follower transistor are held at ground potential and the photodiode and a gate of the pixel source-follower transistor are charged to an initial reset voltage having potential less that of a supply voltage. A second stage of the reset occurs after the initial reset voltage is stored on the photodiode and the gate of the pixel source-follower transistor and the source and drain voltages of the pixel source-follower transistor are released from ground potential thereby allowing the source and drain voltages of the pixel source-follower transistor to assume ordinary values above ground potential and resulting in a capacitive feed-through effect that increases the voltage on the photodiode to a value greater than the initial reset voltage.
    Keywords: Electronics and Electrical Engineering
    Format: application/pdf
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