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  • 1
    Publication Date: 2011-08-19
    Description: This paper introduces new applications and design trade-offs anticipated for free-space optical interconnections of VLSI chips. New implementation s of VLSI functions are described that use the capability of making optical inputs at any point on a chip and take advantage of greater flexibility in on-chip signal routing. These include n-port addressable memories, CPU clock phase distribution, hardware multipliers, and dynamic memory refresh, as well as enhanced testability. Fault tolerance and production yields may be improved by reprogramming the optical imaging system to circumvent defective elements. These attributes, as well as those related to performance alone, will affect the design methodology of future VLSI ICs. This paper focuses on identifying the design issues, their possible solutions, and their impact on VLSI design techniques and, finally, presents some preliminary measurements on various system components.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Optical Engineering (ISSN 0091-3286); 25; 1109-111
    Format: text
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  • 2
    Publication Date: 2013-08-31
    Description: Monolithic diode frequency multiplier arrays, including barrier-N-N(+) (BNN) doubler, multi-quantum-barrier-varactor (MQBV) tripler, Schottky-quantum-barrier-varactor (SQBV) tripler, and resonant-tunneling-diode (RTD) tripler arrays, have been successfully fabricated with yields between 85 and 99 percent. Frequency doubling and/or tripling have been observed for all the arrays. Output powers of 2.4-2.6 W (eta = 10-18 percent) at 66 GHz with the BNN doubler and 3.8-10 W (eta = 1.7-4 percent) at 99 GHz with the SQBV tripler have been achieved.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Michigan Univ., The Third International Symposium on Space Terahertz Technology: Symposium Proceedings; p 595-599
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  • 3
    Publication Date: 2013-08-31
    Description: In the current work, multi-function beam control arrays have been fabricated and have successfully demonstrated amplitude control of transmitted beams in the W and D bands (75-170 GHz). While these arrays are designed to provide beam control under DC bias operation, new designs for high-speed electronic and optical control are under development. These arrays will fill a need for high-speed watt-level beam switches in pulsed reflectometer systems under development for magnetic fusion plasma diagnostics. A second experimental accomplishment of the current work is the demonstration in the 100-170 GHz (D band) frequency range of a new technique for the measurement of the transmission phase as well as amplitude. Transmission data can serve as a means to extract ('de-embed') the grid parameters; phase information provides more complete data to assist in this process. Additional functions of the array beam controller yet to be tested include electronically controlled steering and focusing of a reflected beam. These have application in the areas of millimeter-wave electronic scanning radar and reflectometry, respectively.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Michigan Univ., The Third International Symposium on Space Terahertz Technology: Symposium Proceedings; p 45-57
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  • 4
    Publication Date: 2019-07-27
    Description: This paper reports on the characterization of CMOS detectors for holographic optical interconnects in micro circuits. A VLSI temporal response system has been built, which has high-magnification viewing capabilities to facilitate the identification of the sample area under investigation. An isolated photodiode and load circuit has been characterized to determine responsivity, response time, and light spot positioning effects. The threshold of optical gate cells incorporating the above detectors and a transistor inverter stage to couple to other circuitry has been determined. The rise time and fall time of the optical gate cells have also been determined experimentally. The results were compared with the results of SPICE simulation, and show satisfactory agreement. The time delay of optical gate cell output was thus determined to be 70 ns at 10 microW light input. Threshold power was 0.5 microW light input.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Digital optical computing; Jan. 13, 14, 1987; Los Angeles, CA; United States
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  • 5
    Publication Date: 2019-07-13
    Description: Progress on optically addressing a CMOS RAM for a feasibility demonstration of free space optical interconnection is reported in this paper. The optical RAM chip has been fabricated and functional testing is in progress. Initial results seem promising. New design and SPICE simulation of optical gate cell (OGC) circuits have been carried out to correct the slow fall time of the 'weak pull down' OGC, which has been characterized experimentally. Methods of reducing the response times of the photodiodes and the associated circuits are discussed. Even with the current photodiode, it appears that an OGC can be designed with a performance that is compatible with a CMOS circuit such as the RAM.
    Keywords: ELECTRONICS AND ELECTRICAL ENGINEERING
    Type: Optoelectronic Materials, Devices, Packaging, and Interconnects; Aug 19, 1987 - Aug 21, 1987; San Diego, CA; United States
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